how to make 8 bit in verilog

vead · Sep 22, 2014

hello embers
I want to make port for microcontroller in verilog code
I want to write verilog code for 8 bit port

module port (data_in,data_out )
input[7:0] data_in;
output[7:0]data_out;
wire [7:0]data_out;
endmodule

I think its not enough tell me what I do to make port in verilog I did google but I did not get success

gs65 · Sep 22, 2014

hi,
what is the relation between output and input?
you just define the relation in the code ,that is enough

ads-ee · Sep 22, 2014

As I haven't run across any microcontrollers with a separate input and output data interface bus (parallel peripheral interfaces are usually bi-directional) I've taken the liberty of showing you a bi-directional interface.

At a minimum, with only 1 register in the FPGA would be something like:

Code Verilog - [expand]
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module port (
  inout   [7:0]   data_io,
  input           r__w_n,
  input           enb_n,
  input           clk
);
// rest of code...
endmodule

with multiple registers that need to be accessed you'll also need an address bus:

Code Verilog - [expand]
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module port (
  inout   [7:0]   data_io,
  input   [15:0]  addr,
  input           r__w_n,
  input           enb_n,
  input           clk
);
// rest of code...
endmodule

Note the different syntax for Verilog 2001 port declarations. You should really switch, it's been 13 years since it was introduced and it seems universities (like those in India) seem to be stuck in the HDL stone age.

Regards

how to make 8 bit in verilog

vead

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gs65

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Code Verilog - [expand]
1 2 3 4 5 6 7 8	module port ( inout [7:0] data_io, input r__w_n, input enb_n, input clk ); // rest of code... endmodule

Code Verilog - [expand]
1 2 3 4 5 6 7 8 9	module port ( inout [7:0] data_io, input [15:0] addr, input r__w_n, input enb_n, input clk ); // rest of code... endmodule

how to make 8 bit in verilog

vead

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gs65

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