How to make 2 diffrent clocks work in one module?

[dd2001]

How to make 2 diffrent clocks work in one module?

Expert says Always use one clock domain, since synthsizer easyly to do its job!

but how to convert following code into ONE clock domain




module(....)

output clk_cnt, slow_cnt;

always @(posedge clk or negedge rst) //main clock

if (!rst)
q <= 0;

else
if (q == 4'b1111)
begin
q <= 0;
clk_cnt <= 1;
end
else
q <= q + 1'b1;


always @(posedge slow_clk or negedge rst)

if (!rst)
q_slow <= 0;

else
if (q_slow == 4'b1111)
begin
q_slow <= 0;
slow_cnt <= 1;
end
else
q_slow <= q_slow + 1'b1;


How to output clk_cnt and slow_cnt using main clk?

 

[cdcll]

How to make 2 diffrent clocks work in one moudle?

I would like to know how to set the timing constraint for the different clock domain in the same project? I use qu@rtus.

 

[sweesw]

How to make 2 diffrent clocks work in one moudle?

Design compiler will understand your code, although I was a bit confused

you just need to set_false_path

set_false_path -from find(clock clk) -to find(clock slowclk)
set_false_path -from find(clock slowclk) -to find(clock clk)