How to load verilog and VHDL code into Debussy?

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jamesyang1209

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debussy vhdl

Dear Group,
My project use mixed-language in Modelsim. Now I can dump waveform for debussy. But I don't know how to load verilog(*.v) and VHDL(*.vhd) files into Debussy? It seems Debussy only accept one language at a time.

Thanks.
James.
 

debussy verilog

Hi,

Debussy accepts both verilog and vhdl.
May I know which version of Debussy u are using ?

I can help u solve your problem.

Regards,
Ganesh
 

debussy verilog vhdl

My version is 5.0.v12 (Win95/NT).
Thanks in advance.
James.
 

debussy vhdl verilog

I think you can export your waveform into "vcd" file in modelsim. And then import this file into Debussy as well as do in Simvision.
 

vericom vhdl

uses command tools: vericom & vhdlcom, cpmille your source code into libraries, then load the libraries into debussy
 

load file in verilog

Hi,

just create a file where u have all u'r verilog designs. Then create one more file where u have all u'r VHDL Designs.

verilog.f
----------
1.v
2.v
3.v

Vhdl.f
-------
1.vhd
2.vhd
3.vhd

vericom -f verilog.f
vhdlcom -f vhdl.f

if u dont give any libraries wverything will be compiled in work.lib++

Then invoke debussy.

from file menu import design

Choose from libraries

select work.lib++

Then u can work normally as u work in verilog designs.
 

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