how to limit a glitch voltage...please help

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kakar133

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how to limit a glitch voltage...look at the attachment .. suppose the FET switches are switched on and off properly and their on resistances are very small, how to calculate the minimum value of the decoupling capacitor C1, which will limit the glitch voltage on power supply line to 150m.V Also assume that the high frequency impedance of the power supply line is infinite
 

Can be reduced to a simple capacitance ratio problem, I think. Transistor capacitances that are probably larger than assumed load capacitance have to be considered, too.

Beside being unrealistic, infinite series inductance would involve infinite supply settling time.
 
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how it can be reduced to a simple capacitance ratio problem ? please help...
 

Think about a simple equivalent circuit comprised of capacitors and ideal switches.
 

Re: Very Urgentower supply decoupling Circuit

Hi Kakar,

If the inductive in the supply line is infinitive the capacitor must supply all the switching current your need on the outputs to charge the output capacitance (plus switching current flowing through M1 and M2 during transition). The decoupling capacotor as also a resistor( ESR) which defines then the voltage drop together with the e-function of the capacitor discharge.

Enjoy your design work!
 
Re: Very Urgentower supply decoupling Circuit

thanks for this nice information but how can I find the relationship of the decoupling capacitance with power supply..
 

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