matrixofdynamism
Advanced Member level 2
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Especially since the arrival of high level verification languages, new verification techniques have become mainstream. These include constrained random stimulus generation based testbenches which utilize various methods to record coverage metrics and assertion based testbenches which include the introduction of property specification language based extension of existing languages. All of this also includes the SystemVerilog expansion of the preexisting Verilog language and introduction of things like OSVVM for VHDL.
I am used to writing directed functional tests and for the designs I have worked on so far, it is not clear how to go about applying the advanced methods I mentioned above to verify them. Although I understand the basic ideas behind the advanced verification methods from theoretical perspective, it is not clear how to put them into practice.
What should I do to get a practical understanding of how to use constrained random stimulus and assertion based testbenches? One thing could be to observe several projects where this has been implemented, but then I work with VHDL and do not know SystemVerilog or UVM. What would be the most reasonable thing to do going forward?
I am used to writing directed functional tests and for the designs I have worked on so far, it is not clear how to go about applying the advanced methods I mentioned above to verify them. Although I understand the basic ideas behind the advanced verification methods from theoretical perspective, it is not clear how to put them into practice.
What should I do to get a practical understanding of how to use constrained random stimulus and assertion based testbenches? One thing could be to observe several projects where this has been implemented, but then I work with VHDL and do not know SystemVerilog or UVM. What would be the most reasonable thing to do going forward?