xihuwang
Member level 2
Re: How to layout the mos capacitor to decrease gate leakage
Hi:
I am working on a pll . When the leakage current of the capacitor
of the LPF above 100nA, the pll 's performance will not be accepted.
So, I want to know :
1. how much are the gate leakage for a 50pF mos cap in 0.13um ,0.25um ,0.35um process
2. How to layout the mos cap to decrease the leakage? Does decrease the unit
cap 's area make sense ?
Added after 2 minutes:
Any help docs ?
Thanks forwards !
Hi:
I am working on a pll . When the leakage current of the capacitor
of the LPF above 100nA, the pll 's performance will not be accepted.
So, I want to know :
1. how much are the gate leakage for a 50pF mos cap in 0.13um ,0.25um ,0.35um process
2. How to layout the mos cap to decrease the leakage? Does decrease the unit
cap 's area make sense ?
Added after 2 minutes:
Any help docs ?
Thanks forwards !