how to layout 150mA output PMOS

I am designing a 150mA output current regulator. how can i layout the the large size Pmos. I reverse a die, whose drain and source is tapezoid. which advantge is it.

hey can you send me the reversed schematics! i am always interested in peoples reversing technique - are you stripping layers and using photographs?



to answer your question, power mos shapes like waffle, hexagon, and snake increase the W while keeping the area constant - ie more power in the same area.

the drawback is ESD and snapback - having corners in your die means you have to add offset on the drain side or field concentration will cause early breakdown and bad esd performance and early wearout.


for 150mA driver, I wouldn't worry too much about using straight s-d bars as in the normal mosfet layout. now 2A drivers, that's a different story!

what's your minimum length? if 1um, i'd add 1/2um of setback to enhance esd protection. if less than 1um, you'll need to add more setback.

Sorry, i look the die in the microscope.

I think the layout help to increase the ESD performance. Because the Pmos width is very larger, then from current density of the pmos input is larger than output. So the width of drain input is more larger. By the way, there is no ESD protection, but the other pin have ESD protection. Which I think that better Pmos ESD performance is one reason. our length is 0.6um. Ithink the distance between contact to poly should be enough small to keep the small vds at large cuurent. I am thinking now, how to layout our PMOS, i think the size should be different with reverse layout because different process. What is the principle of the size design. who have any advice, please share with us? thanks!

haha - i never thought of this problem! actual w/l is harder to find when reversing trapezoid because of the strange layout! that is another good idea for power mos..

to your question - basically you just need to calculate the on-resistance of a 150mA switch in your process, and use that instead of working on this strange layout. i think i calculated 1200/0.5u as a 100mA pmos - can you try that first, then increase W as needed for 0.6u.





ps - are you able to send some photographs just to me? i do dc-dc so linear regulators aren't my competitor - this one is all yours! i would just like to see some other reversing techniques

Thanks for your reply.

Since the PMOS is applied for Low dropout regulator, the Vds is required very low (about 0.2V at output current 150mA). So the width of PMOS is larger than 1200. I use 12000um/0.6um. My main problem is how to design the width of drain(or source) at input teminal and output terminal, and the distance between drain(source) contact to polar. Thanks again!

For 0.6um pmos, I'd put about 1um setback between the gate and s/d contact to prevent esd damage, that should pass 2kV at least.

so 12000 * 2.6u => 31ku^2. or somewhere around 47 square mils. not too bad. i suggest setback on both the s/d sides because your device will have to resist esd zaps from both sides.

Hi ,
When u talk about layout that how to do layout of PMOS having rating of 150mA, U must take care about the drain and source areas and how much metal width u maintaining.

so ,
Maintain proper metal width according to current rating. and by using more metals in parallel U can do layout of more current rating also in less area and by maintaing more vias u can reduce the resistance also. Dont maintain minimum dimen for S/D areas,take more area and connect them with more metal width by keeping more vias.