How to know whether a design is RTL or GATE

[hok]

Hi all,

I am newbie to EDA domains and to this forum...

How can I know a design is RTL or GATE? People talked also about netlist, what is it?

Thanks

 

[gokulka]

hi,
A sequential design with clock is RTL and a combinational design is gate level.

 

[jducluzeau]

Hi,

RTL is your code you write in verilog or VHDL.
Gate is the netlist after synthesis. We talked about netlist too.
It is easy to see the difference. In netlist, there is no loop, no if. The tool which synthesize translate the RTL code in netlist to map sone primitive instances like and,or,buf,mux etc.

When you talk a simulation at RTL level it based on the code before synthesis.
Gate level simulation is based on the netlist after synthesis and timing.

There is nothing to see with sequential and combinatorial .

Regards,
Jerome

 

[Rogov]

You are wrong, gokulka .

RTL. RTL description of the device is a model (like mathematical model). RTL describes behaviour of the device. That's why RTL-model is also called "behavioural" model. But usually RTL doesn't deal with real implementation of the device. Moreover, not every RTL can be realizable on a chip. This RTL is called "not synthesisable".
RTL "features". RTL deals with objects like: wire, register, variable, event.

Gate & Netlist. Gate and Netlist usually mean the same. We get Gate from RTL after synthesis stage. Gate describes your device in terms of a real electric circuit. So a register from RTL is translated into a trigger, that has at least 5 pins: data_in, data_out, clock and of course supply (VSS, VDD). And there is no confidence we can get Gate from RTL. Example: try to implement RTL-structure "forever" by means of real electric gates...
Gate "features". Gate deals with objects like: wire and gates (triggers, AND, OR, XOR, invertors, buffers and other "real" gates that you can just buy in a store ).

---------- Post added at 23:25 ---------- Previous post was at 22:19 ----------

NB: It's not mandatory for Gate to have supply (Power/Ground or VSS/VDD) representation. Actually there is a special kind of Gate which gates have P/G pins.
Usually P/G pins are omitted in Gate.

 

[hok]

Jerome, merci pour tes explications

gokulka, Rogov: thank you for your posts.

I got confused these last days because we have a big design and people say that it is gate-level design but when I look into it, some of DUs are RTL (code containing if statements,...). After your explanations, I discussed again with them and they said... well it is not fully gate level design.