How to interface cpld with fpga?

[bhuvasen]

Hi friends,
I'm a new bee of interfacing the cpld and fpga. here i'm using the cpld xc95144xl and fpga is spartan-3 xc3s400-tq144. somebody give me suggestion over that how to interface those things. if i give PROM ,xcf02s how prom interface take place..

Regards
Sen chett.

 

[Big Boy]

The PROM goes to the FPGA alone. The CPLD doesn't need PROM, and is programmed via JTAG, on it on-board non-volatile RAM (flash). There's no special arrangement imposed to the chips layout, but on the programming side, you should just daisy-chain the JTAG chain.

That is, you link together all the TMS, TCK and TRST, and from the programming JTAG header, you go from the header pin named TDI to the first chip TDI, then, from that chip TDO to the next chip TDI, then from that TDO to the last chip TDI, and from that last chip TDO back to the JTAG header pin labled TDO.

In the chain, you can put any chip first, but usually, since the PROM and FPGA are related, it would be logical to chain them next to each other.

 

[bhuvasen]

Reg material for interface...

Hi friends..

Here i do my board design for one of optics application. in my design i have cpld and fpga.. cpld is xc95144xl and fpga is spartan-3 xc3s400-tq144. I want to draw the pin details of each and one and to interface those things.. i have spartan-3 pin details .. but for cpld i didn't have.. And also pls tell me which pins i have to give more importance while interfacing. Pls give me sme suggestions... If there any materials reg that pls provide me link...

Regards

Sen chett..

 

[Big Boy]

For interfacing PROM to FPGA, the best way is probably to look at schematic of designs already made. You can check other Spartan schematics too, as the programing interface doesn't change much.

The pinout for each devices will most probably be found on Xilinx site. Also look for application notes on interfacing the PROM to FPGA, I don't know if such doccuments exist.

Things to check at first hand is the powers. The Spartan-III have several power source (A global 3.3V, 2.5V and 1.2V and user-defined voltage for each of the 8 banks). Also, when the FPGA configure itself from the PROM, it use 2.5V IO, and then switch to whatever is on that bank. So, if you have 3.3V IO, the FPGA will still configure at 2.5V from the PROM. There's an application note on Xilinx site showing how it's still possible to use 3.3V for that bank (involving using resistors).

I'm sorry I don't have the links though...