In the data sheet(AD7656) they have not given any specific protocol and I am Using Altera Max II and regarding width I dont understand what is width in parallel interface
In the data sheet(AD7656) they have not given any specific protocol and I am Using Altera Max II and regarding width I dont understand what is width in parallel interface
Clarifies that you need to learn more about digital logic to manage the project.
The datasheet actually explains a lot. The interface can be either configured as parallel 16 bit data bus or as three channel SPI. You have to implement either one or the other in MAX II. Both is basically possible.
You didn't yet mention how the ADC data will be processed in your programmable logic and what's their final target.
Clarifies that you need to learn more about digital logic to manage the project.
The datasheet actually explains a lot. The interface can be either configured as parallel 16 bit data bus or as three channel SPI. You have to implement either one or the other in MAX II. Both is basically possible.
You didn't yet mention how the ADC data will be processed in your programmable logic and what's their final target.
sir,Actually they told to study the parallel interface(AD7656) timing diagram and the Altera max II CPLD has to generate those signals to ADC(AD7656).This is the information they gave me.And I really dont know what to concentrate and where to concentrate also.
sir,Actually they told to study the parallel interface(AD7656) timing diagram and the Altera max II CPLD has to generate those signals to ADC(AD7656).This is the information they gave me.And I really dont know what to concentrate and where to concentrate also.
So many "they"s. Is this project forced on to you?
Best way would be to take it part by part.
1> Learn more about Altera Max (read datasheet)
2> Then concentrate how the FPGA is communicating with its peripherals. You focus should be either of the one interfaces as explained in post #4 (read protocol datasheet)
3> Lean about AD7656 as to how it communicates (read datasheet)
4> Before beginning with Verilog............
I am quiet confused with one particular thing.I was instructed to write the coding for the timing diagram (Parallel interface) of AD7656.My doubt is the in the timing diagram the last signal is the transfer of databits DB0 to DB15.But the diagram portrays as if it is sending analog signals such as V1,V2,V3,V4,V5,V6.How to read this analog signals using verilog?
Clarifies that you need to learn more about digital logic to manage the project.
The datasheet actually explains a lot. The interface can be either configured as parallel 16 bit data bus or as three channel SPI. You have to implement either one or the other in MAX II. Both is basically possible.
You didn't yet mention how the ADC data will be processed in your programmable logic and what's their final target.
Sir The project is a part of the sonar receiver.Where the receiver receives Sound waves as input and those sound waves need to be transferred to digital. For this purpose A FPGA and ADC is used.The receiver is an hydrophone array.
There are 16 individual data lines...
The ADC is called 16 bit ADC...
Can you imagine any other number than 16?
(The ADC theoretically could make it complicated and slow and use the 2 x 8 bit mode - figure 26. I don't recommend this)
*******
The parallel interface is as simple as can be: just a 16 bit DFF for each channel.
If this is a problem for you you should decide to start with more simple FPGA projects.
* input a single pushbutton with the use of a single DFF
* input four pushbutton with a quad DFF
* input 16 ADC data lines with a 16xDFF
Or do you see the problem in setting up an FSM to generate the ADC control signals?