How to instantiate two different modules based on a condition in verilog?

[Sudeep Mc]

I have got two different multiplier modules.
1. 4x4 multiplier
2. 8x8 multiplier
Based on the length of the inputs a and b, one of these modules should be selected. I have written a code where enable becomes high when any of the input length is greater than 4 bit(binary). I cannot instantiate a module inside if or case statement and not even inside an always block. I tried using generate blocks. Since the parameter value is fixed, in all the cases it chooses only one of the modules. I donot know how to use `define,`ifdef `elseif. Please do let me know, how can i acheive this logic in verilog and also the use of generate and `define,`ifdef `elseif.

With regards,
SUDEEP M C

 

[saadbinshafique]

You can generate enable output, use it wisely. You can make an enable pin in the verilog code of 4x4 and 8x8 multiplier. Connect this enable directly to multipliers.
Lets make it easy. For example, you want to use 4x4 multiplier if enable=0 and 8x8 multipplier if enable =1.
In top module, connect 8x8 module directly with enable pin and connect 4x4 multiplier with enable using a NOT gate.
Then, if enable will be 0, 4x4 multiplier will come into action. and if enable will be high, 8x8 multiplier will be active.