How to instantiate two different modules based on a condition in verilog?

Sudeep Mc · Mar 13, 2014

I have got two different multiplier modules.
1. 4x4 multiplier
2. 8x8 multiplier
Based on the length of the inputs a and b, one of these modules should be selected. I have written a code where enable becomes high when any of the input length is greater than 4 bit(binary). I cannot instantiate a module inside if or case statement and not even inside an always block. I tried using generate blocks. Since the parameter value is fixed, in all the cases it chooses only one of the modules. I donot know how to use `define,`ifdef `elseif. Please do let me know, how can i acheive this logic in verilog and also the use of generate and `define,`ifdef `elseif.

With regards,
SUDEEP M C

FvM · Mar 13, 2014

Are you asking about a parameterizable module, where the bit length of some inputs is defined by a parameter, or do you mean that the length is variable at runtime? A generate construct can only work for the first case.

Code:

generate
if (SIZEPAR == 8)
// instantiate 8x8 multiplier 
else
// instantiate 4x4 mutiplier
endgenerate

Sudeep Mc · Mar 13, 2014

FvM said:
Are you asking about a parameterizable module, where the bit length of some inputs is defined by a parameter, or do you mean that the length is variable at runtime? A generate construct can only work for the first case.

Code:

generate if (SIZEPAR == 8) // instantiate 8x8 multiplier else // instantiate 4x4 mutiplier endgenerate

In the generate-if case given above, SIZEPAR is fixed. Therefore it will always instantiate 8x8 multiplier. If the input size is 4 and lesser it has to instantiate 4x4 multiplier. I doubt that will happen.
Yes, I mean the length of the inputs are variable at runtime. In that case what do you do?

Code:

module opt(m,a,b);
parameter aw=8, bw=8;
input [aw-1:0] a;
input [bw-1:0]b;
output [aw+bw-1:0]m;
reg en;
always@(a,b)
begin
if(a[7]|a[6]|a[5]|a[4]|b[7]|b[6]|b[5]|b[4])
en<=1'b1;
else
en<=1'b0;
end

generate
if(aw==8)
m8x8(m,a,b);
else
m4x4(m,a,b);
endgenerate

[/QUOTE]
even in the above case, It will always instantiate 8x8 block. There is no flexibility.
What I mean is, Depending on the size of the input at the very instant(runtime), It should decide between these modules.

With regards,
SUDEEP M C

TrickyDicky · Mar 13, 2014

You cannot have variable length at runtime. You need to make the length the worst case possible.

How to instantiate two different modules based on a condition in verilog?

Sudeep Mc

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How to instantiate two different modules based on a condition in verilog?

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