How to instantiate an ADC module in verilog-AMS?

ruwan2 · Mar 25, 2015

Hi,
I learn verilog-AMS with SMASH. After I follow a simple example project pll, I create an ADC project (copy this module from the LRM). In the .pat file I have the substantiation:

.lib "source.vams"

adc1 0 src1 out adc NLO=VSS NHI=VCC
xvsrc1 src1 0 sinVarFreq freq=5.5e1 coeff=4.0

but it always has the error message:

ERROR: ADC1: cannot set value 'src1' for parameter 'NLO'
ERROR: ADC1: cannot be instantiated (none model name 'adc' definition is found)

The definition of NLO is:

Parameters description
NLO
Name of net for voltage representing logic 0.

I cannot figure out how to make this adc module work.

Here is the adc module file:

module adc(in, clk, out);
parameter bits = 8, fullscale = 1.0, dly = 0, ttime = 10n;
input in, clk;
output [0:bits-1] out;
electrical in, clk;
electrical [0:bits-1] out;
real sample, thresh;
integer result[0:bits-1];
genvar i;
analog begin
@(cross(V(clk)-2.5, +1)) begin
sample = V(in);
thresh = fullscale/2.0;
for (i = bits - 1; i >= 0; i = i - 1) begin
if (sample > thresh) begin
result = 1.0;
sample = sample - thresh;
end
else begin
result = 0.0;
end
sample = 2.0*sample;
end
end
for (i = 0; i < bits; i = i + 1) begin
V(out) <+ transition(result, dly, ttime);
end
end
endmodule

Here I modify a sine wave generator as a clk signal output:

`include "disciplines.vams"
`include "constants.vams"

module sinVarFreq(p, n);

inout p, n;
electrical p, n;

parameter real freq = 1.0e2;
parameter real coeff = 1.0;
real tempr;

analog begin
V(p,n) <+ (sin(`M_TWO_PI * freq * (0 + 1.0) * $abstime) > 0) ? 1 : -1;
end
endmodule

Click to expand...

Thanks,

How to instantiate an ADC module in verilog-AMS?

ruwan2

Member level 5

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How to instantiate an ADC module in verilog-AMS?

ruwan2

Member level 5

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