How to insert library function to find sum.....

[Sreya39]

Hi,
I want to find the variance of 20 numbers....For that first i have to find the sum of 20 nos..... I have given my verilog code below. There is no synthesis errors....but i am not getting the sum..... Does it works if library file (Arithmetic) is included...
If so how to include library function.
Or there anyother way to solve this problem....
help me please...

Thanks and Regards,
Remya:|:|:|

module meansum(clock,Enable, corrouti1,corrouti2,corrouti3,corrouti4,corrouti5,corrouti6,corrouti7,
corrouti8,corrouti9,corrouti10,corrouti11,corrouti12,corrouti13,corrouti14,corrouti15,
corrouti16,corrouti17,corrouti18,corrouti19,corrouti20,sum);
input clock,Enable;
input [9:0] corrouti1,corrouti2,corrouti3,corrouti4,corrouti5,corrouti6,corrouti7,
corrouti8,corrouti9,corrouti10,corrouti11,corrouti12,corrouti13,corrouti14,corrouti15,
corrouti16,corrouti17,corrouti18,corrouti19,corrouti20;
output [9:0] sum;
reg [14:0] sum ;
initial sum = 0;
reg [9:0] r1[0:19];
integer i;
always @(posedge clock) begin
if (Enable)
r1[0]= corrouti1;
r1[1]= corrouti2;
r1[2]= corrouti3;
r1[3]= corrouti4;
r1[4]= corrouti5;
r1[5]= corrouti6;
r1[6]= corrouti7;
r1[7]= corrouti8;
r1[8]= corrouti9;
r1[9]= corrouti10;
r1[10]= corrouti11;
r1[11]= corrouti12;
r1[12]= corrouti13;
r1[13]= corrouti14;
r1[14]= corrouti15;
r1[15]= corrouti16;
r1[16]= corrouti17;
r1[17]= corrouti18;
r1[18]= corrouti19;
r1[19]= corrouti20;
end
always @(posedge clock) begin
i=0;
while (i<20) begin
assign sum = sum + r1;
i=i+1;
end
end
endmodule

 

[sameem_shabbir]

First of all u r doing mistakes regarding register size

U r trying to add 20; "10 bit" nos and u have assigned only 10 bit length to sum output.

input [9:0] corrouti1,corrouti2,
output [9:0] sum; ?????????????????????

So first of all increase ur output length to at least 16* output [15:0] sum;

Moreover do chk if while is synthesizable

and for summing all the 20 nos; i think, dont go in detail of writing code
just write the expressinon
sum = corrouti1+corrouti2...................corrouti19+corrouti20;

What i think is that project navigator should replave the + sign with adder circuitary. Try it. I hope it should work




*(binary--1111111111 > 1023-- decimal) and (1023*20 > 20460) so sum should be able to accomodate 20460 as the worst case senario