[SOLVED] how to initialize an array with zeros in verilog

Mina Magdy · Jun 19, 2013

please i want to know how to initialize an array with zeros case when i do this

for(i=0;i<9000;i=i+1)
begin
parity=0;
end

it gives me this Loop count limit exceeded. Condition is never false.
please help thanks in advance

mrflibble · Jun 20, 2013

To get around this specific limitation do:

Right mouse button on "Synthesize - XST" ==> Process Properties => Synthesis Options => Other XST Command Line Options => and then add this option: "-loop_iteration_limit 12345"

And don't forget to put it in an initial block, so something like:

Code Verilog - [expand]
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integer i;
initial begin
    for (i=0;i<9000;i=i+1) begin
        parity[i]=0;
    end
end

And this is all assuming that you chose this particular method because there is no other cleaner method to initialize it. And I am also assuming that when you say initialize, you actually mean initialize. Some other ideas as inspiration:

Code Verilog - [expand]
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reg [8999:0] parity = 0; // This will also initialize it with zero's, no loop required
reg [8999:0] more_parity = {4500{2'b10}}; // initialize with 101010.... pattern

This will synthesize just fine, and will fill those flip-flops with the required initial values.

Mina Magdy · Jun 20, 2013

thanks thats help me alot

[SOLVED] how to initialize an array with zeros in verilog

Mina Magdy

Member level 3

mrflibble

Advanced Member level 5

Mina Magdy

Mina Magdy

Member level 3

Similar threads

Code Verilog - [expand]
1 2 3 4 5 6	integer i; initial begin for (i=0;i<9000;i=i+1) begin parity[i]=0; end end

Code Verilog - [expand]
1 2	reg [8999:0] parity = 0; // This will also initialize it with zero's, no loop required reg [8999:0] more_parity = {4500{2'b10}}; // initialize with 101010.... pattern

[SOLVED] how to initialize an array with zeros in verilog

Mina Magdy

Member level 3

mrflibble

Advanced Member level 5

Mina Magdy

Member level 3

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