How to indicate overflow of 4017 counters? How to stop counter?

[truffaldino]

How to indicate overflow of 4017 counter? How to stop counter?

Is it possible to force 4017 to set some "flag" indicating the overflow afrer just one full cycle: E.G. to turn an indicator LED on afrer one full cycle and then keep this LED switched on permanently. The "carry" pin of the 4017 is high only half of the full cycle, so one needs to use some trick.

I need this to count number of pulses from a circuit consisting of two 555 (First 555 is set periodic. It is modulated by the second one-shot 555), just to know if the pulses were counted properly without an overflow.

 

[BradtheRad]

Re: How to indicate overflow of 4017 counter? How to stop counter?

then keep this LED switched on permanently.

An ordinary RS flip-flop can do this job. Made from two cross-coupled transistors. Set it to light an led when output pin #1 goes high for a second time.

And how do we prevent it from triggering the first time it goes high? With a delay that resets the flip-flop for a several cycles. The delay can be made from a capacitor-resistor network.

 

[d123]

Re: How to indicate overflow of 4017 counter? How to stop counter?

Hi,

You could AND pin1 and pin10 output with an inverter off pin1 into the AND, when 1 is low and 10 is high it could trigger a flipflop. This is dumb logic, beware...

I think more reliable is using a counter IC like the CD4026 or CD4033 that is clocked with the above AND solution. Or, why not just use a second CD4017 and clock it from the AND solution? The "clock inhibit" pins on the 4017/4026/4033 look fun to think about how they may assist in the objective when combined with another signal.

If the circuit sees multiple clock cycles for the first 4017 that's a fair bit more complicated I think.

- - - Updated - - -

...A fair amount of combinational logic and thinking about what combinations will be failsafe is needed to avoid false positives.

 

[KlausST]

Re: How to indicate overflow of 4017 counter? How to stop counter?

Hi,

In my eyes an RS flip flop won't work as you expect.
A RS flip flop is level sensitive thus it will be activated at the first couple of clocks.
You need an edge triggered flip flop, it should be activated at the rising edge only.

Without knowing how you expect it to be reset and what supply voltage you use....we can't give good assistance.

Klaus

You could AND pin1 and pin10 output with an inverter

According to my datasheet
Pin1 = output "5"
Pin10 = output "4""
...I can't find out how this should work...

 

[d123]

Re: How to indicate overflow of 4017 counter? How to stop counter?

Hi Klaus,

Okay, I explained badly. When 4017 output 1 is low and 10 is high, 1 into a NOT then into an AND input 1 and 4017 output 10 into AND input 2, could be used to trigger clock on second 4017, using that output 1 to light LED.
Still wouldn't explicitly represent "overflow", i. e. 11 clock pulses in first 4017... Need to think about this better maybe.

 

[d123]

Re: How to indicate overflow of 4017 counter? How to stop counter?

Hi,

There's actually an unbelivably easy solution to this idea that only requires one additional CD4017. Especially as CD4017s aren't sold separately but in packs of 5, 10, 25, etc.



You know this device needs a POR on the reset pin, I guess.

Hope it's a good solution for you.

 

[d123]

Hi,

Proof of pudding and all that...

I've never liked the 4017 model in Tina, it seems glitchy and worse - calls pin 12 pin 13 in error checks (hmmm, nice work there...), it seems unpleasantly put together and doesn't seem to coincide completely with the CD4017 datasheet. If you ignore all that and adapt to its frustrating oddness, it'll do for simulations to show an idea. BTW, for the first half hour it showed the first output #1 high at T = 0/pulse #1 and again at pulse #11, then after adding and removing an RC POR, with the exact same circuit it stopped showing pulse #1. FFS. Anyway.

 

[d123]

I'm curious as to why the datasheet is clear that the CD4017B triggers/advances on a positive going/rising edge, whereas the TINA model triggers/advances on a falling edge.