How to increases Maximum operating freqency

library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity map1 is
port(clk:in std_logic;
reset:in std_logic;
code_rate:in std_logic_vector(3 downto 0);
mod_mode_sel:in std_logic_vector(1 downto 0);
N_ldpc:in std_logic_vector(15 downto 0);
input1:in std_logic;
out_Rut std_logic_vector(15 downto 0);
out_Iut std_logic_vector(15 downto 0));
end map1;

architecture arch of map1 is


subtype select_1_2 is integer;
type select_e is array (0 to 2, 0 to 63) of select_1_2;
constant e:select_e:= ((7,1,4,2,5,3,6,0, 7,1,4,2,5,3,6,0, 11,7,3,10,6,2,9,5,1,8,4,0, 11,7,3,10,6,2,9,5,1,8,4,0, 15,1,13,3,8,11,9,5,10,6,4,7,12,2,14,0, 7,3,1,5,2,6,4,0) , (0,5,1,2,4,7,3,6, 7,1,4,2,5,3,6,0, 2,7,6,9,0,3,1,8,4,11,5,10, 11,7,3,10,6,2,9,5,1,8,4,0, 2,11,3,4,0,9,1,8,10,13,7,14,6,15,5,12, 7,3,1,5,2,6,4,0) , (7,1,4,2,5,3,6,0, 7,1,4,2,5,3,6,0, 11,7,3,10,6,2,9,5,1,8,4,0, 11,7,3,10,6,2,9,5,1,8,4,0, 7,2,9,0,4,6,13,3,14,10,15,5,8,12,11,1, 7,3,1,5,2,6,4,0));

type select_16 is array (0 to 3) of std_logic_vector(15 downto 0);
signal Zq_16:select_16:= ("0011110010110111", "0001010000111101", "1011110010110111", "1001010000111101");

type select_64 is array (0 to 7) of std_logic_vector(15 downto 0);
constant Zq_64:select_64:= ("0100010100100000", "0011000101100000", "0000100111100000", "0011001101010000", "1100010100100000", "1011000101100000", "1000100111100000", "1011001101010000");

type select_256 is array (0 to 15) of std_logic_vector(15 downto 0);
constant Zq_256:select_256:= ("0100100110100000", "0011111111001111", "0010110000101101", "0011010111111110", "0000010011101000", "0000111010111001", "0010001001011100", "0001100010001010", "1100100110100000", "1011111111001111", "1010110000101101", "1011010111111110", "1000010011101000", "1000111010111001", "1010001001011100", "1001100010001010");

signal rate : integer range 0 to 4;
signal mod_sel : integer range 0 to 63;
signal SET : integer range 0 to 16;
signal b: std_logic_vector(31 downto 0);
signal count: integer range 0 to 33;
signal flag : std_logic;

begin


flag <= '0' when reset = '1' else '1' when count = SET+SET ;

---here "0001" is for code rate 3/5 , "0010" for code rate 2/3 and "0000" for all others....

rate <= 0 when code_rate ="0000" else 1 when code_rate = "0001" else 2 when code_rate = "0010" else 0 ;

---depending on the modulation format and N_ldpc value index going to change--------
mod_sel <= 0 when (mod_mode_sel = "01" and N_ldpc="1111110100100000") else
8 when (mod_mode_sel = "01" and N_ldpc="0011111101001000") else
16 when (mod_mode_sel = "10" and N_ldpc="1111110100100000") else
28 when (mod_mode_sel = "10" and N_ldpc="0011111101001000") else
40 when (mod_mode_sel = "11" and N_ldpc="1111110100100000") else
56 when (mod_mode_sel = "11" and N_ldpc="0011111101001000") ;

---- selecting number of substreams--------------
SET <= 2 when mod_mode_sel = "00" else
8 when mod_mode_sel = "01" else
12 when mod_mode_sel = "10" else
16 when (mod_mode_sel = "11" and N_ldpc="1111110100100000") else
8 when (mod_mode_sel = "11" and N_ldpc="0011111101001000");

process(clk, reset)
begin
if reset = '1' then
count <= 0;

elsif rising_edge(clk) then
if count = SET+SET then
count <= 1;
else
count <= count + 1;
end if;
end if;
end process;

process(clk, reset , flag)
variable i: integer ;
variable j: integer ;

begin

if reset = '1' then
b <= (others=>'0');
i := 0;
j := 0;

elsif rising_edge(clk) then

if (mod_mode_sel /= "00" and (count >= 1 and count <= SET+SET)) then

b( e(rate , mod_sel+i) + j ) <= input1;
i := i + 1 ;


if i = SET then
j := j + SET ;
i := 0 ;
end if;

if j = SET+SET then
j := 0 ;
end if;


end if;
end if;
end process;


process (clk)
variable sel_1: std_logic_vector(3 downto 0);
variable sel_2: std_logic_vector(3 downto 0);

begin
if rising_edge(clk) then

------Mapping for QPSK----------

if mod_mode_sel = "00" and count >= 1 then
if input1 = '0' then
out_r <= "0101101010000010" ;
out_i <= "0101101010000010" ;
elsif input1 ='1' then
out_r <= "1101101010000010" ;
out_i <= "1101101010000010" ;
end if;
end if;

-------Mapping for both 16-QAM ,64800/16200 and 256-QAM , 16200 ---------
if mod_mode_sel = "01" or (mod_mode_sel = "11" and N_ldpc="0011111101001000") then

if count = 9 then

sel_1 := "00" & b(0) & b(2) ;
out_r <= Zq_16(to_integer(unsigned(sel_1)));

sel_2 := "00" & b(1) & b(3) ;
out_i <= Zq_16(to_integer(unsigned(sel_2)));

end if;

if count = 13 then

sel_1 := "00" & b(4) & b(6) ;
out_r <= Zq_16(to_integer(unsigned(sel_1)));

sel_2 := "00" & b(5) & b(7) ;
out_i <= Zq_16(to_integer(unsigned(sel_2)));
end if;

if flag = '1' and count = 1 then

sel_1 := "00" & b(8) & b(10) ;
out_r <= Zq_16(to_integer(unsigned(sel_1)));

sel_2 := "00" & b(9) & b(11) ;
out_i <= Zq_16(to_integer(unsigned(sel_2)));
end if;

if flag = '1' and count = 5 then

sel_1 := "00" & b(12) & b(14) ;
out_r <= Zq_16(to_integer(unsigned(sel_1)));

sel_2 := "00" & b(13) & b(15) ;
out_i <= Zq_16(to_integer(unsigned(sel_2)));
end if;
end if;

-------Mapping for 64-QAM and 64800/16200---------

if mod_mode_sel = "10" then
if count = 13 then

sel_1 := '0' & b(0) & b(2) & b(4) ;
out_r <= Zq_64(to_integer(unsigned(sel_1)));

sel_2 := '0' & b(1) & b(3) & b(5) ;
out_i <= Zq_64(to_integer(unsigned(sel_2)));
end if;

if count = 19 then

sel_1 := '0' & b(6) & b(8) & b(10) ;
out_r <= Zq_64(to_integer(unsigned(sel_1)));

sel_2 := '0' & b(7) & b(9) & b(11) ;
out_i <= Zq_64(to_integer(unsigned(sel_2)));
end if;

if flag = '1' and count = 1 then

sel_1 := '0' & b(12) & b(14) & b(16) ;
out_r <= Zq_64(to_integer(unsigned(sel_1)));

sel_2 := '0' & b(13) & b(15) & b(17) ;
out_i <= Zq_64(to_integer(unsigned(sel_2)));
end if;

if flag = '1' and count = 7 then

sel_1 := '0' & b(18) & b(20) & b(22) ;
out_r <= Zq_64(to_integer(unsigned(sel_1)));

sel_2 := '0' & b(19) & b(21) & b(23) ;
out_i <= Zq_64(to_integer(unsigned(sel_2)));
end if;

end if;

-------Mapping for 256-QAM and 64800---------

if (mod_mode_sel = "11" and N_ldpc="1111110100100000") then
if count = 17 then

sel_1 := b(0) & b(2) & b(4) & b(6) ;
out_r <= Zq_256(to_integer(unsigned(sel_1)));

sel_2 := b(1) & b(3) & b(5) & b(7) ;
out_i <= Zq_256(to_integer(unsigned(sel_2)));
end if;

if count = 25 then

sel_1 := b(8) & b(10) & b(12) & b(14) ;
out_r <= Zq_256(to_integer(unsigned(sel_1)));

sel_2 := b(9) & b(11) & b(13) & b(15) ;
out_i <= Zq_256(to_integer(unsigned(sel_2)));
end if;

if flag = '1' and count = 1 then

sel_1 := b(16) & b(18) & b(20) & b(22) ;
out_r <= Zq_256(to_integer(unsigned(sel_1)));

sel_2 := b(17) & b(19) & b(21) & b(23) ;
out_i <= Zq_256(to_integer(unsigned(sel_2)));
end if;

if flag = '1' and count = 9 then

sel_1 := b(24) & b(26) & b(28) & b(30) ;
out_r <= Zq_256(to_integer(unsigned(sel_1)));

sel_2 := b(25) & b(27) & b(29) & b(31) ;
out_i <= Zq_256(to_integer(unsigned(sel_2)));
end if;

end if;
end if;

end process;

end arch;


when I synthesized its give 87MHz in Spartan 3A-DSP.

pls help me......

Presently the worst performance restrictions are caused by
- using unconstraint integers for i and j
- using variables instead of signals for i and j, resulting in cascaded arithmetic