How to increases frequency of the VHDL design

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RAVI30

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HI...
I m implementing LDPC encoder for DVB-T2 as a my final year project , I have implemented but it giving 73MHz(I have using SPARTEN-3A DSP FPGA) frequency but i need 100MHz frequency, so plz help me to increases the frq
 

The output of DCM (Digital Clock Manager) gives various frequencies. You can get 100MHz from DCM.

 

What is giving 73Mhz? the timing analyser? have you given it a 100MHz timing spec?

Or you have provided 73MHz and you now need to provide 100 MHz?
 

I have synthesized my LDPC block code in xilinx ISE tool after synthesized it is giving 73.0753MHZ freq...
 

That sounds like the fmax of your system - ie. the maximum frequency you could provide before timing errors will occur.
With a 73MHz fmax, it sounds like you do not have much pipelining in the design. The solutions would be to provide some 100 MHz timing specs, run the timing analyser and look for the failing paths and fix them (usually by increasing the pipelining).
 

You can look at synthesis report and check what path is the main cause of your low frequency. Just open your synthesis report and search for "data path", you will have the worst path in you design.

Similarly, you can check for the worst path also in Post-PAR Static timing report, after place and route.
 

Minimum period: 13.685ns (Maximum Frequency: 73.071MHz)
Minimum input arrival time before clock: 6.880ns
Maximum output required time after clock: 5.248ns
Maximum combinational path delay: 1.342ns

this my synthesized report.....
 

You can either set the clock frequency to 100 MHz and check which pathes report timing failures or review a detailed timing analysis of the present design and locate the most critical pathes.

Then try to restructurize the critical pathes with pipelining.
 

k thank you

- - - Updated - - -

i have used Xilinx IP memory core so in placing and routing it giving error....
 

RAVI30 said:
Minimum period: 13.685ns (Maximum Frequency: 73.071MHz)
Minimum input arrival time before clock: 6.880ns
Maximum output required time after clock: 5.248ns
Maximum combinational path delay: 1.342ns

this my synthesized report.....
Click to expand...

Look at the text below this, the good hint is after this point. You will see a source and a destination , so you can check the critical path of your project. In order to speed your circuit up, you have to optimize this path (reducing unneeded circuit, pipelining, finding alternative ways of coding or alternatives designs).
 

RAVI30

Do you have a ucf timing constraint file? How about a xcf timing constraint file for XST? If not then you should have both. I get the distinct impression you might have no ucf file as that is the type of report you get when you don't have a ucf file (a description of the maximum frequencies, 14.7 just spits out a bunch of tables for inputs, outputs, and clock periods only)

Add both a ucf (map/par) and an xcf (xst) then see what the tools report as the worst case path. Also you might want to look at the path in the schematic view to determine what the logic looks like after xst synthesizes your RTL. Simple single lines of code can easily explode into 10+ levels of logic if you don't understand what the synthesizer will do to implement it.

Regards
 

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