How to increase the phase margin of the OP AMP

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thnk u safwat, i got there is different between SR but still how to adjust it, all the transistors symmatric (also the bias circuit) what u advice me to do?
regards
 

well, i THINK (but not sure) if this is a SC application then this discrepancy can be neglected if both settle to the right accuracy (i.e. if the absolute error spec is met then the relative error can be neglected)
 

haaaa, i cannt do that bcz one of the output has settling time bigger than the max setlling time, so what u think about it, in fact the ota should get less than 20 ns for 50 MSPs, while i got one 10ns and the other 50 ns, big gab
regards
 

well, i didn't think that the difference is that large, so i think a good thing to do is that u should investigate why this large discrepancy so plot the current in all main branches and see why one is settling less (why not getting the same charging/discharging current), but u will eventually need to enhance this settling behavior which is already seems dominated by the bad SR so if this SR is just bad, then fix it by pumping more current (can be at the expense of the other SR, so take from the good one and put in the bad one)
but to be sure, see if this SR is the limiting factor by comparing the settling behavior in the good one by the bad one (to see if it is really spending to much time slewing)
 

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    wael_wael

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thank u safwat for ur help, i am so happy i found some one he likes to help others, i will double chick hole circuit and see where is the problem
by the way for Pmos differential input, it must to get nagative volt as input or not?
also i want to till u that the two boost AMP in the circuit above with PMOS diff input, is that right, or i should chang the boost amp feeding the NMOS to NMOS diff input? the thing maks me crazy that is all the symmetric transistors have same current and same VDS, so i am guessing the problem comes from the boost amp, are u agree with that?.
best regards
 

by locating non dominant poles so far from the dominant pole u can increase the phase margin
 

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    wael_wael

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increase the current and reduce the gain.

But all are trade off.
 

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