How to increase the phase margin of the OP AMP

[wael_wael]

hi every body

first of all let me till u from my a little experience that the Gain , phase margin and the settling time or slew rate is most important parameters for any OP AMP utilizing in A/D converters, in fact is there any technique to increase the phase margin with out effect the settling time or the gain.
best regards

 

[Old Nick]

No.

analogue design is about trade-off's, you just have to find the best balance for the application you intend the amp for.
The closer the amp is to instability, the greater the slew rate and settling time - usually.

 

[onakaitai]

How about using OTA instead of OPA?

 

[rajanarender_suram]

How about using OTA instead of OPA?

It depends on ur usage OTA-lower Cap loads only

OPA-high Cap and resistive loads

 

[analog_prodigy]

OTA can give low power dissipation

 

[wael_wael]

The OTA can get high phase margin and SR by increasing the current (increase the power) and increase the CAP load,

 

[ee_ykhab]

Phase Margin , gain , bandwidth are all correlated with each other.
Phase Margin(in frequency domain) can reflect the actual settling time (in time domain) at the same time given that slew rate is unlimited. Of course, slew rate will also govern your max. slope of your response as a result your settling time 2.

Thus, choosing the opamp topology is important and ppls normally try to increase the phase margin by doing pole zero cancellation or splitting complex poles.

 

[hazemafify]

Of course this is good solution, but the best one is to replace MOS in triode instead of the resistive load.

How about using OTA instead of OPA?

It depends on ur usage OTA-lower Cap loads only

OPA-high Cap and resistive loads

 

[wael_wael]

thank u guys, i am still have small question that is, when i do the settling time test, how much the Vinput should be? is it small input or high input.
regards

 

[xuedashun]

generally small input (say, 10mV) is used to check settling time, large input (1V) to check slew rate

 

[wael_wael]

thanx, my problem i have fully differential OTA with gain boosting amp, why the settling time has big different (30n ) between the two outputs, while all the transistors symmetric.
regards

 

[safwatonline]

maybe if u post the schematic some one could help

 

[wael_wael]

here the OTA
the gain boost opamp is fulyy differential withe PMOS input
regards

 

[wael_wael]

is it correct the Vinput of the OTA above are positive volt, it should be negative, right?
regards

 

[safwatonline]

it is kind of unreadable schematic

 

[FvM]

it is kind of unreadable schematic

Absolutely! I suggest preprocessing images and reviewing before posting them. Irfanview is a simple and effective tool for image processing - or windows paintbrush. https://www.irfanview.net

 

[safwatonline]

thanx, my problem i have fully differential OTA with gain boosting amp, why the settling time has big different (30n ) between the two outputs, while all the transistors symmetric.
regards

i guess this can happen if the SR+ is not equal to SR-

 

[Sadegh.j]

No, the compensation capacitance slows down the circuit as one of our prof said: "THERE IS NO FREE LUNCH"

cheers

 

[wael_wael]

thank u so much, cap there i can remove it but still the settling time is not same for diff output. other side if SR is not equale, ok i gree with that but why? if all the sizes same

 

[safwatonline]

u are slewing from different current sources , i.e. charging and discharging paths are different.
think of it as if the source of asymmetry is the input signal, so if u put the opposite signal u will get the same kind of discrepancy but at the different side.
i.e. when Vinp=Vhigh and Vinm=Vlow u get SR+=X and SR-=X+delta Vop-Vom=V
and when Vinp=Vlow and Vinm=Vhigh u also get SR+=X and SR-=X+delta but the output is reversed such that Vop-Vom=-V
thats what the symmetry help you.