How to improve this low side FET driver?

[uoficowboy]

Hi - I'm trying to build a discrete low side FET driver. My plan is to use it to drive a FET as part of a fairly fast DC/DC boost converter (probably switching at 250KHz). Thus I'm looking to minimize rise and fall times on the gate of the FET.

Please see the attached LTSpice schematic and simulation results. I'm seeing around 70ns rise and fall times. Not horrendous, but not awesome either. The diode is there to keep the BJT from saturating. I tried diodes in the same place on the other two BJTs but it did not seem to help much if at all. The one diode I have on there doesn't seem to make that big a difference, either.

I've also included the spice files that you need to run the simulation.

Can anybody suggest a means of improving the rise and fall time of this circuit?

Thanks so much!

 

[dick_freebird]

First thing, BJT saturation models are not to be trusted.
Especially if the transistor is not sold as a "switching"
transistor. And even if, the behavior may not be fitted
across all force-beta, Vce, Ic possibilities, temperature
and so on.

The output emitter followers, will probably benefit from
transient saturation so long as the minimum pulse width
us greater than saturation recovery time. I made use
of this in a power MOSFET driver IC design with a similar
output stage (more buffered, but still).

You might interpose a diode between the upper and lower
base resistors to bring yourself out of cutoff some.

Your simulation should be able to tell you where the
risetime comes from. Just look at the final base node
and output node; if they slew at similar rates you
are base drive limited and if the base is sharper than
output, you are gain or Rc limited against the load.

The Q1/D1 combo wants a Schottky with a decently
low Vf, the Miller capacitance of Q1 against the 5K/100pF
base feed may be part of what slows the output base
risetime. Play with the base impedance looking into Q1
and see what a bare drive gets you.

Personally I'd spend the buck and a half on a power
MOSFET driver IC and call it done. There's only so many
times you can design a gate driver out of transistors
and call it interesting.

 

[alexan_e]

What do you think of a circuit like



input is driven by 250KHz 3v3
green trace is input (left axis)
red trace is load current (right axis)

Alex

 

[uoficowboy]

First thing, BJT saturation models are not to be trusted.
Especially if the transistor is not sold as a "switching"
transistor. And even if, the behavior may not be fitted
across all force-beta, Vce, Ic possibilities, temperature
and so on.

The output emitter followers, will probably benefit from
transient saturation so long as the minimum pulse width
us greater than saturation recovery time. I made use
of this in a power MOSFET driver IC design with a similar
output stage (more buffered, but still).

What do you mean by transient saturation? I'm not familiar with that term.

You might interpose a diode between the upper and lower
base resistors to bring yourself out of cutoff some.

You're saying that a careful placement of this diode could keep VBE on the output NPN from going too low, right? How exactly is it connected? Maybe it's just too early in the morning - but I'm having trouble seeing how that would work.

Your simulation should be able to tell you where the
risetime comes from. Just look at the final base node
and output node; if they slew at similar rates you
are base drive limited and if the base is sharper than
output, you are gain or Rc limited against the load.

The risetime seems to be from the first NPN, the BC846. The gate of the FET follows the collected of this transistor quite closely. The fall time, however, is limited by something else, it would appear.

The Q1/D1 combo wants a Schottky with a decently
low Vf, the Miller capacitance of Q1 against the 5K/100pF
base feed may be part of what slows the output base
risetime. Play with the base impedance looking into Q1
and see what a bare drive gets you.

The diode was chosen because I've used it in a previous design and was happy with how fast it was. It quotes Vf=.34V @1ma, .7V@30ma. Not good enough? When you say that I should play with the base impedance, you mean R2||C1, right? I have tried adjusting those values quite a bit but the current ones seemed to speed things up the most.

Personally I'd spend the buck and a half on a power
MOSFET driver IC and call it done. There's only so many
times you can design a gate driver out of transistors
and call it interesting.

I'm really just after the challenge of building a good FET driver. This is for a non-commercial one or two-off project so I thought I'd give myself a learning opportunity instead of using a black box. Sorry for all the dumb questions.

 

[uoficowboy]

What do you think of a circuit like

View attachment 62224

input is driven by 250KHz 3v3
green trace is input (left axis)
red trace is load current (right axis)

Alex

Hi Alex! Sorry for the slow response. I was unable to find a model for the diode that you used (that part doesn't appear to be made anymore - or at least supported) so I just used the same diode that I used in my last simulation.

Rise time seems to be somewhat worse than in the circuit I posted, but fall time is improved. See attached.

I haven't spent much time playing with this yet but thought I'd show you the results I'm seeing to see if they match with what you're seeing.

 

[alexan_e]

The value of R2 is 1K in my example schematic , try to lower that resistor (to 500 or even lower) to provide a higher base current and you will get faster turn on times due to the higher current provided to the mosfer gate.
The diode I have uses was a random Schottky diode, you can change any component in the circuit (respecting the current ratings).

Alex

 

[FvM]

I think, it's rather hard for your simple BJT circuit to compete with an industry standard gate driver like TC427. This is mainly due to the fact, that CMOS circuit technology offers very obvious advantages for this application. External BJT boosters come into play, if you need to extend the gate current above 1 or 2 A (although IC gate drivers with up to 12 A drive current are available now). But you have to choose transistors with sufficient current gain at high currents.

Means like schottky clamps are basically effective, but the overall circuit has to be carefully designed. I also agree with dick_freebird, that you shouldn't be too sure about the accuracy of basic SPICE models in saturated switching. You should check first, if the respective gummel-poon parameters have been actually entered.

 

[alexan_e]

The improved TC4426A/4427A/4428A are even better
Side By Side - Product Comparison (TC427 TC4427A)

And the 3A models TC4423A/4424A/4425A
TC4424A

Alex

 

[uoficowboy]

I think, it's rather hard for your simple BJT circuit to compete with an industry standard gate driver like TC427. This is mainly due to the fact, that CMOS circuit technology offers very obvious advantages for this application. External BJT boosters come into play, if you need to extend the gate current above 1 or 2 A (although IC gate drivers with up to 12 A drive current are available now). But you have to choose transistors with sufficient current gain at high currents.

Means like schottky clamps are basically effective, but the overall circuit has to be carefully designed. I also agree with dick_freebird, that you shouldn't be too sure about the accuracy of basic SPICE models in saturated switching. You should check first, if the respective gummel-poon parameters have been actually entered.

Hi FvM - would I be able to build a faster circuit with discrete FETs? I have no particular need to use BJTs here, just that I've had better experiences with making BJT circuits fast rather than FET circuits.

Thanks!

 

[FvM]

Designing CMOS cicruits from discrete devices would result in a higher component count. An important point in CMOS IC design is to scale the transistor areas of stages appropriately. You'll also have difficulties to find suitable small complementary FETs for the input stages.

What's your motivation for designing a discrete gate driver? It looks somewhat like re-inventing the wheel.

 

[uoficowboy]

Designing CMOS cicruits from discrete devices would result in a higher component count. An important point in CMOS IC design is to scale the transistor areas of stages appropriately. You'll also have difficulties to find suitable small complementary FETs for the input stages.

What's your motivation for designing a discrete gate driver? It looks somewhat like re-inventing the wheel.

Hi FvM - my interest in building a good gate driver is because I figured it'd be good practice for designing with transistors instead of black boxes

 

[uoficowboy]

I just realized one important problem with the design I originally posted. alexan_e's circuit suffers from the same problem. Both drivers burn a constant amount of power when the FET is off. I would much prefer a design that burned a constant amount of power when the FET is *on*. The reason being that this is driving the primary switch in a boost converter that has a high ratio of Vout/Vin, thus the FET will be off significantly more than it will be on.

With that in mind - are either of our circuits modifiable in a way that causes the driver to burn more power in the on cycle than in the off?

Thanks!

 

[FvM]

I think, your latest post puts another question mark over the "good design practice" idea. It reminds the simple fact, that you can hardly compete with modern CMOS circuit technology in terms of efficiency.

I agree, that there are some fields of application, where discrete circuits have their eligibility besides "black boxes". I see it particularly in those places, where no integrated circuits with suitable properties are available.

 

[alexan_e]

I just realized one important problem with the design I originally posted. alexan_e's circuit suffers from the same problem. Both drivers burn a constant amount of power when the FET is off. I would much prefer a design that burned a constant amount of power when the FET is *on*. The reason being that this is driving the primary switch in a boost converter that has a high ratio of Vout/Vin, thus the FET will be off significantly more than it will be on.

With that in mind - are either of our circuits modifiable in a way that causes the driver to burn more power in the on cycle than in the off?

Thanks!

I agree with your point but note that the circuit I have presented can have 10-20 times lower consumption because the resistor is in the base of the transistor driving the totem pole (so you will have current gain) instead of directly in the base of the totem pole like in your circuit.
In addition if you select better transistors with higher gain then this resistor can be lowered, for example

predriver
8050SL

totempole
2SB772
2SD882

Actually your circuit already had high gain output transistors but with lower current capacity so the comparison wasn't fair, I had low gain BD transistors, try it with the same transistors in both circuits.

Alex

 

[uoficowboy]

I agree with your point but note that the circuit I have presented can have 10-20 times lower consumption because the resistor is in the base of the transistor driving the totem pole (so you will have current gain) instead of directly in the base of the totem pole like in your circuit.
In addition if you select better transistors with higher gain then this resistor can be lowered, for example

predriver
8050SL

totempole
2SB772
2SD882

Actually your circuit already had high gain output transistors but with lower current capacity so the comparison wasn't fair, I had low gain BD transistors, try it with the same transistors in both circuits.

Alex

Hi Alex! You are right - switching up the two output transistors makes a world of difference. Once I do that, your circuit has specs just like mine, except the fall time is faster on yours. I can get mine to match by decreasing the base resistor on the PNP. By the way - I also noticed that I had the PNP in backwards when I did the last simulation of your circuit. Oddly enough, the circuit still worked fine. Very strange

I don't understand what the diode in your circuit does. I can't see its use. I tried removing it from the circuit and the simulation results did not seem to change. I would actually expect results to improve with it removed - it seems like it would slow down turn off and potentially even keep the gate from getting fully drained.

With the diode removed, the functionality of your circuit becomes more clear. It is much like mine, except with the extra NPN on top to speed up turn on. So I would think that you would want high hfe and low output capacitance, which it looks like the part you selected has. Is that accurate?

It is strange to me that the simulation is showing your and my circuit as being equally fast (and that is with the resistors matched in value). With the extra NPN on top I'd expect yours to be faster. Maybe I should not put full faith in the simulation?

---------- Post added at 06:57 ---------- Previous post was at 06:56 ----------

I think, your latest post puts another question mark over the "good design practice" idea. It reminds the simple fact, that you can hardly compete with modern CMOS circuit technology in terms of efficiency.

I agree, that there are some fields of application, where discrete circuits have their eligibility besides "black boxes". I see it particularly in those places, where no integrated circuits with suitable properties are available.

Hi FvM - I'm not trying to follow good design practice. Just trying to improve my skills. My work provides me with more than enough time to follow good design practice! I am quite confident that I could find a black box that would blow away anything I can come up with with discretes. But where's the fun in that?

 

[alexan_e]

I don't understand what the diode in your circuit does. I can't see its use.

Removing the diode would short the base and emitter of Q10 so removing it is like removing the transistor.

Alex

 

[FvM]

Hi FvM - I'm not trying to follow good design practice. Just trying to improve my skills. My work provides me with more than enough time to follow good design practice! I am quite confident that I could find a black box that would blow away anything I can come up with with discretes. But where's the fun in that?

I didn't bring in the good design practice term, but this sounds more comprehensible to me. It's not so much fun however, if your handmade gate driver will be finally beaten by a distance from industry standard ICs, although it involves higher part count and power dissipation.

If you want 10 ns range rise and fall time, you typically need GHz fT transistors. Another question is, if your power circuit is really prepared for the switching speed you're trying to achieve. It may be the case, that you'll want to slow it down, if you observe the waveforms in your real circuit (not the perfectly inductance free simulation design).

 

[uoficowboy]

Removing the diode would short the base and emitter of Q10 so removing it is like removing the transistor.

Alex

Oh yeah! I missed that

And somehow I messed up when I thought I had run the simulation with the diode removed. Removing the diode approximately doubles the turn on time.