how to improve the INL of Pipelined ADC

[wdd]

Hi, guys,
With the test resutls of my ADC, the DNL and INL are
DNL: -0.5LSB – 0.5LSB
INL: -2.5LSB – 2.5LSB
as you can see, the INL is worse. But i know little about
the mechanisms of INL, can anybody give some advices?

Thx a lot,
Best Regrads,
wdd

 

[zenisle]

inl is not important for adc

 

[kobeii]

zenisle: why did you say that ?

 

[suhas_shiv]

I assume you are doing more than one stage. Try to design the first stage with as less errors as possible. See if you have the correct reference voltages and see the output for stage one only and then proceed.
A good pipeline ADC has an INL < 0.5LSB.

 

[maxwellequ]

There are a number of mechanisms that originate INL errors in pipelined ADCs (mismatch in the capacitors, opamp gain and settling errors, poor vref generation, ....). I suggest you search some PhD/MsC thesis on the net (this is a topic with many available references).

What you should have done, before designing the ADC, was to understand all these phenomenons and derive the specifications for the pipeline stages. For example how did choose the gain of the opamps? How have you sized the capacitors ?

I think that to solve your problem, you must understand the linearity limitations of the architecture, in order to understand what you must re-design....

But, if you want help, it would a good idea to post more details about the architecture you used, ADC specs (resolution, fs, fin), show pictures with the test results... Do the results improve if you lower fin or fs ?

Regards

PS: zenisle, you don't know what you are talking about