sjamil02
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Hi All,
I have designed LDO with NMOS pass transistor with 35mV dropout (1V supply regulated down to 0.965V). Since the dropout voltage is small then my PSRR is bad (-38dB @dc and 0db @10MHz). Furthermore the NMOS pass transistor is sized in triode region (to get smaller device and small dropout). To improve the psrr @dc, I have increase the gain of the error amplifier (I'm using folded cascode structure with Vdd=2.5V). It works and the psrr is slightly improved from -38dB --> -44dB. But this is not enough since i am targeting psrr = -69dB @dc. If I further increased the error amplifier gain, I'm afraid the bandwidth will be too low. Is there any other way to improve the dc psrr? Secondly, how to improve psrr at high frequency (10MHz)? I do not have luxury to increase the output capacitance. My target is psrr > -30dB @10MHz.
Please help.
Thanks in advanced
Sj
I have designed LDO with NMOS pass transistor with 35mV dropout (1V supply regulated down to 0.965V). Since the dropout voltage is small then my PSRR is bad (-38dB @dc and 0db @10MHz). Furthermore the NMOS pass transistor is sized in triode region (to get smaller device and small dropout). To improve the psrr @dc, I have increase the gain of the error amplifier (I'm using folded cascode structure with Vdd=2.5V). It works and the psrr is slightly improved from -38dB --> -44dB. But this is not enough since i am targeting psrr = -69dB @dc. If I further increased the error amplifier gain, I'm afraid the bandwidth will be too low. Is there any other way to improve the dc psrr? Secondly, how to improve psrr at high frequency (10MHz)? I do not have luxury to increase the output capacitance. My target is psrr > -30dB @10MHz.
Please help.
Thanks in advanced
Sj