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to set the VLT of oscillator to Vdd/2, and set the charge and discharge current of the ring/gate to the same. Or you can use a buffer to modulate the duty.
You can make a oscillator with 2Mhz ,
This signal devide by 2 with digital divider (1/2).(with Flip-flop )
This you can get 1Mhz 50% duty cycle signal.
You can make a oscillator with 2Mhz ,
This signal devide by 2 with digital divider (1/2).(with Flip-flop )
This you can get 1Mhz 50% duty cycle signal.
Ya, thanks guys, I know we can obtain 50% duty cycle by divide by two.
But now, 2MHz is not avaliable, so I would like to know any popular
method to get 50% duty cycle?
Calaulate the time btw clock "H" and "L" period by RC structure, and comparing by
each cycle. adjusting duty cycle by one step(maybe xxns) depend on the result above. continue first step.
Generate a short pulse (impulse) for each rising and falling edge. You have then effectively doubled the frequency. Now you can divide/2 to get your 50% duty cycle. It is easy to make an edge detector with RC and inverter gate. Then OR the pulses from 2 gates to get the X2 output for the F/F.
Ya, thanks guys, I know we can obtain 50% duty cycle by divide by two.
But now, 2MHz is not avaliable, so I would like to know any popular
method to get 50% duty cycle?
PLL didn't control the duty cycle, but instead it will give u 2*f clock which is only depent on the rising edge of ur input clock.
By doing this, u can do a div by 2 to get exactly 50% duty cycle.
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