How to improve coverage of shadow logic testing?

[akrlot]

memory shadow logic

The test of the shadow logic that surrounds the memory gives a low coverage.The memory is modeled as a black box. is there a way to improve coverage(using tetramax and design vision)
Thx in advance

 

[omid219]

shadow_wrapper

Put some registers at input/output ports of memory and make a dummy mapping between them in test mode. This makes the combinational logics in memoy boundary controllable & observable. In normal mode these dummy registers are bypassed.

 

[akrlot]

Re: shadow logic testing

thx for reply. is there a way to create the registers automatically with synopsys tools (design vision,tetramax)...i tried to do this automatically with design vision:
( see design vision menu :Test->autofix->shadow logic DFTwrapper ) or by the command : set_dft_configuration -shadow_wrapper. but i get the same coverage when i export the netlist to tetramax.

 

[atremp]

Re: shadow logic testing

I think you should not only set the "set_dft_configuration -shadow_wrapper", but also point out the memory cell and the corresponding ports of this memory cell.

for example:
set_wrapper_element top_module/I1/I2/memory_cell_instance_name
set_port_configuration -cell memory_cell -clock CLKA
......(for all ports)

detailed information please refer to the latest SOLD document in Test Automation folder.

 

[akrlot]

Re: shadow logic testing

thanx all for reply.
I wasnt able to do that with DFTC i have to insert test points manually!

 

[akrlot]

Re: shadow logic testing

any other opinions?

 

[zhustudio]

shadow logic testing

create a ram model, so it can be recoginized by ATPG tools. so the shadow logic can be tested or use macrotest method. it can be implemented in mentor DFT tools or tetramax

 

[atremp]

shadow logic testing

I think that special memory models are now available which can help complete the shadow logic testing without any addition flipflop insertion.

 

[gold_2007]

Re: shadow logic testing

how to do this in mentor graphics

 

[scorp_nn]

Hi! I'm using DFT Compiler C2009 version, so commands set_port_configuration & set_wrapper_element is not available there. Anybody know how to do the same in this version of DFTC? I have the same problem of low coverage caused by memory. Thanks a lot!

 

[ConradATPG]

Re: memory shadow logic

Is the untested logic between the RAMs and shadow logic? Does your design use BIST to test your RAMs? If so then this portion of the shadow logic is most likely tested by the BIST. Ask your BIST vendor about the coverage.

If the faults are between the non-RAM logic and shadow logic then you need to investigate the DFT associated with the shadow logic. Can values from the circuit be captured by the shadow logic, can values from the shadow logic drive your circuit and are the shadow logic flip-flops scanned? Look at the shadow logic to see if this is possible and look at the simulation of your vectors to see if it is happening.