How to import Date and Time from PC to VHDL codes?

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Port Map

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Hi.
I want to have an automatic version for my codes, then I want to import Date and Time from OS to my VHDL code.
Is this possible to do something like that?

I'm using xilinx ISE on Win7.
very thanks for replies.
 

Port Map said:
Hi.
I want to have an automatic version for my codes, then I want to import Date and Time from OS to my VHDL code.
Is this possible to do something like that?

I'm using xilinx ISE on Win7.
very thanks for replies.
Click to expand...

I dont think you can do it with ISE.
You are going to need other script or software
To manage your vhdl file.
 

you will need to run a TCL script that modifies your code in some way. Easiest would be a constant in a package that is connected to a read register.
 

TrickyDicky said:
you will need to run a TCL script that modifies your code in some way. Easiest would be a constant in a package that is connected to a read register.
Click to expand...

have a look at the following code :

**broken link removed**

i guess you can find many similar examples.
 

Alternatively you can build your ISE projects from a Makefile. Then add a rule to update the vhdl file with date & time in it. Essentially it's the same mechanism as that tcl example ... generate a vhdl file with datetime in it.
 

look into the USR_ACCESS component. This can be loaded with a 32b value during bitgen, and bitgen even has a date/time option built in.

In the HDL, the component has 3 output ports, two of which are unused. Just hook up the 1 remaining port somewhere in the HDL where the PC can access it. This part is up to you -- either some PCIe, ethernet, usb, rs232, etc... interface.

At a more complex scale, you can also use data2mem with BRAM to load BRAMs after/during bitgen. With some extra logic, you can store more than just date/time -- things like repository version, build tool versions, timing score, top-level generics, utilization levels, etc...

The advantage of these methods, especially with ISE, is that no source changes between builds.

edit --
https://www.xilinx.com/support/documentation/application_notes/xapp497_usr_access.pdf -- for USR_ACCESS
 
Last edited:
Neat. That USR_ACCESS does seem to be limited to virtex-5/6/7 though.

Strictly speaking, the auto generated .vhdl file doesn't require a source code change between builds either. Yes yes I know, vhdl file, and it changes. But auto generated files are (well should be) 1) not in the code repository and 2) not even in your regular source path where all your other vhdl/verilog files live.
 

mrflibble said:
Alternatively you can build your ISE projects from a Makefile. Then add a rule to update the vhdl file with date & time in it. Essentially it's the same mechanism as that tcl example ... generate a vhdl file with datetime in it.
Click to expand...

Can you plz tell more about creating Makefiles? where can I learn more about it?
Is there any example available for this method?

Which method can be easier? MakeFile or Tcl Script?

- - - Updated - - -


"USR_ACCESS can be configured with a 32-bit user-specified value or automatically loaded by
the bitstream generation program (BitGen) with a timestamp." ...

So,
I'm interesting in using this method and I Liked it. But sometimes, the projects is not on virtex-5/6/7 and USR_ACCESS cant be used.
 

Port Map said:
Can you plz tell more about creating Makefiles? where can I learn more about it?
Is there any example available for this method?
Click to expand...

Google "xilinx ise makefile" for some examples.

Which method can be easier? MakeFile or Tcl Script?
Click to expand...

That depends on what you already know. If you happen to be a tcl wizard, then tcl. If you happen to have used makefiles in dozens of previous projects, then makefile.

If you have to start from scratch, tcl is probably easier. Setting up a good Makefile can take some time. But IMO it's worth it, since you can use it for future projects as well. And you don't need to press buttons in ISE to do a build.
 

I visited the link below and changed it to have a package file that contains my version information ,
but I should run a TCL command manually every time that I want to synthesize the project.
Problem is that some times I forget to do that. I'm using GUI to implement my design and I've not found any way to run a TCL for every synthesize automatically.
If there is any way please help. If NO, I think using Makefiles could be a better choice.

**broken link removed**
 

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