How to implement VHDL grammer in TCL

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asjoshi

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Hi,
I'm building a utility, which is nothing but a fast, crude synth tool in TCL language. The main aim is to find out flop pairs on clk-domian boundries. Besides, it may provide ino such as Number of flops, max combi logic level, etc per entity basis. This utility will b applicable to Design files only, and not TB files.
For this, i need to read and understand VHDL file. Currently I'm using TCL searching methods to get identifiers like IF-THEN-ENDIF, etc. But is there any VHDL grammer available readymade, for TCL.
I know, such grammer is available for lex-yacc, but I want to stick to TCL. Any info in this direction will b appreciated...

-asjoshi.
 

read into design compiler then report it.
 

Hi papertiger,
Could u xplain ur last post with some more details? That may help me a lot.

-asjoshi
 

What is purpose of your Tcl utility?
Maximum combinational logic level (and even a Flop number) depends from synthesis results (and is different for different synthesis constraints) and could not be found from RTL code. Maybe you do some estimation of those things?
Probably your utility loose it’s purpose if you load design into DC (or do the synthesis and load it into PT), and then use DC or PT to report whatever you want and scripts to extract something from those reports – but it is probably the easiest way to solve it.
 

Hi andromeda,
The main aim of the utility is to work fast, without any scripting. Actual synth by DC/PT may take few dayz in many of our proj. So this will be fast estimation utility. It will give approximate info. This is actually required in scalable IPs.

Also it was designed to chk flop-pairs on clk-domain boundries. It's a kind of design chk. I'm just thinking of adding some features like, max combi-logic level, etc.

The TCL implementation of LEX is called TcLex. Is anybody aware of it. I've dwnlded the TcLex pkg, trying to learn it. Plz help me if anybody has worked on it b4.

-asjoshi.
 

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