How to implement open collector logic in VHDL?

[yamaha]

hi

how to implement open collector logic in VHDL,

regards
yam

 

[dk614nd]

Re: Open collector

use and gate

 

[tkbits]

Re: Open collector

If you're interfacing to an external connection that requires open collector characteristics (e.g., PS/2 interface), then you can simulate open collector buffers with 3-state buffers:

out_signal <= '0' when in_signal = '0' else 'Z';