how to implement LPM_RAM_DQ in verilog

lpm_ram_dq

i had written the following code for LPM_RAM_DQ (type of RAM in Altera MAXPLUSII) in verilog :


// LPM_RAM_DQ
module LPM_RAM_DQ (DATA, ADDRESS, WE, INCLOCK, OUTCLOCK, Q);

//parameter Note = "RAM with Separate Input and Output Ports";
parameter LPM_WIDTH = 8;
//parameter LPM_TYPE = "LPM_RAM_DQ";
parameter LPM_WIDTHAD = 8;
parameter LPM_NUMWORDS = "UNUSED";
parameter LPM_FILE = "UNUSED";
parameter LPM_INDATA = "UNREGISTERED";
parameter LPM_ADDRESS_CONTROL = "REGISTERED";
parameter LPM_OUTDATA = "UNREGISTERED";
//parameter LPM_HINT = "UNUSED";
input[7:0] DATA;
input[7:0] ADDRESS;
input WE;
input INCLOCK;
input OUTCLOCK;
output[7:0] Q;
//reg[LPM_WIDTH - 4'd1:0] Q;
parameter REGISTERED = 1'b0;
parameter UNREGISTERED = 1'b1;
parameter REGISTERED_ENUM_LPM_ADDRESS_CONTROL = 1'b0;
parameter UNREGISTERED_ENUM_LPM_ADDRESS_CONTROL = 1'b1;
parameter REGISTERED_ENUM_LPM_OUTDATA = 1'b0;
parameter UNREGISTERED_ENUM_LPM_OUTDATA = 1'b1;

endmodule




// RAM
module RAM (
address,
we,
inclock,
outclock,
data,
q);

input [7:0] address;
input we;
input inclock;
input outclock;
input [7:0] data;
output [7:0] q;

wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];

lpm_ram_dq lpm_ram_dq_component (
.outclock (outclock),
.address (address),
.inclock (inclock),
.data (data),
.we (we),
.q (sub_wire0));
defparam
lpm_ram_dq_component.intended_device_family = "FLEX10K",
lpm_ram_dq_component.lpm_width = 8,
lpm_ram_dq_component.lpm_widthad = 8,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "REGISTERED",
lpm_ram_dq_component.use_eab = "ON",
lpm_ram_dq_component.lpm_hint = "MAXIMUM_DEPTH=256",
lpm_ram_dq_component.lpm_type = "LPM_RAM_DQ";


endmodule



after i write the code, i syhthesis it using Synopsys FPGA Express. but the following error occur :

Error: syntax error at or near token '.' (File: E:/Testing for CPU Nabil/3 try/NabilCPU.v Line: 237) (VE-0)


can anyone help me out!!! thanks !!!