How to implement long channel device (layout and schematic)?

[lovseed]

I am designing an 14-bit DAC which requires to use long channel devices say w=6.72u l=38u. But the SPICE model just has LMAX=10u, and PDK also has the max length limit of 10u.


(1)I am wondering whether there will be some problem if I use such a long channel device.
(2) And how about the layout? Just draw a long channel or with folded gate as presented in some paper? what will be the advantage or disadvantage?

B.R.

 

[archillios]

depend on your technology.
you can use snake pdiff, under whole square gate poly.
Such long-channel device is used as linear resistor, right?

 

[jerryzhao]

Re: How to implement long channel device (layout and schemat

I draw the MOS in series (the SPICE model just has LMAX=10u) when I design circuit POR. Layout fold as schematics.
I don,t know why you use the such device in DAC. Which block you use such device.

 

[mists]

this long channel devive maybe is used as current source for current-steering DAC with very large output impedence.

 

[lovseed]

Re: How to implement long channel device (layout and schemat

I draw the MOS in series (the SPICE model just has LMAX=10u) when I design circuit POR. Layout fold as schematics.
I don,t know why you use the such device in DAC. Which block you use such device.

Some question about draw the mos in series:
(1)for the series , all gate are connected, right?
(2)for all the series, the substrate all connected to vdd(if pmos) or just connect to the source to eliminate body-effect.
(3)if the series number of pmos with w/l is N , does it really equivalent to one pmos with w/(N*l)?

In my view, at least item(2) will make some difference in performance.

B.R


why I am using long channel devices?

I am calculating the min area needed for current source from the INL_yield and foundry mismatch-parameters. And since my design is 14-bit , the w/l ratio is very small for 1LSB, which cause the channel very large.

Hope my description makes things clear.

 

[gururajb]

I got what you said wrt DAC area for unit cell based on INL.
I am also trying to design a 10 bit DAC taking into account INL, DNL and mismatch parameters.
For the 1X unit cell(LSB), I am trying to use two series connected pmos devices.
But I am not able to get the correct value of current. Why ?
With the same biasing circuit I am able to get the correct value of current for 2X LSB cell.

Can anybody give some inputs.