How to Implement Dynamic Clock Gating Without Using Combinational Logic in an AXI4-Based SoC?

[roronoazoro]

I am working on implementing dynamic clock gating in an AXI4-based SoC for power optimization. I want to ensure that the design avoids combinational logic in the clock gating path to prevent glitches and timing issues.

Details:

• The clock gating needs to be controlled based on AXI4 signals like valid, ready, or transaction counters.
• Using combinational logic directly in the clock enable path can lead to glitches and unreliable behavior.
• I am looking for a clean and safe approach that adheres to best practices for clock gating.

Requirements:

1. The implementation should use sequential logic for clock enables.
2. It must integrate with standard clock gating cells (if applicable).
3. It should comply with AXI4 protocol behavior for control signals.

What is the best method to implement dynamic clock gating in this scenario?

I would appreciate if someone could share their experience, recommended design patterns, or relevant code examples.

 

[BradtheRad]

It's hard to be sure from your terminology whether this is adequate for your needs.... AND logic admitting or blocking a clock from getting through. It can also be built from diodes-resistors-transistors: