[SOLVED] How to implement digital trimming for CMOS Voltage References

[rmanalo]

Hello everyone,

I've read that trimming is a post-fabrication adjustment technique, but I like to show the trimming method through simulation using only ideal switches for now. I've been struggling with trimming my voltage reference in simulation in the SS corner. The first try I tried to use a simple ideal switch shown.

I used a g-element in hspice to model the switch, the voltage-controlled-resistor varies from a minimum of 100u-ohm to 100g-ohm. The results have no change because at open circuit (100g-ohm) there is still a connection.


The second try I used a path selector as shown

Still using g-element switch model for the two swtiches, the results were unsatisfactory (400ppm/C instead of 80ppm by independently adding parallel transistors at SS Corner).


The last one is not a digital trimming method as it uses fuses as shown

So far this is my best option but I cant simulate a fuse in hspice.

From here I have a few questions
1. are there any more methods for me to try? What are good references or books that tackle and explain digital trimming in detail, such as a full circuit
2. I used ideal switches in this case, it makes me wonder if implementing this as a circuit will have worse results
3. Is implementing fuses a good idea for a 4 bit trim range? (concerning on the number of trimming pads)

 

[frankrose]

Instead of fuses use transmission gates. https://en.wikipedia.org/wiki/Transmission_gate

 

[dick_freebird]

Or, fuses controlling transmission gates.

Fuse reliability has to be proven at some expense and you
may or may not be at that foundry on that flow.

Unless you want a digital host and all that neediness,
you need some sort of nonvolatile element. That may
be in the current path, or may control the current
path.

Parallel shunt trim enjoys the best FET Ron uniformity.
Ladders with FETs at differing body-source potential
add a bit of process sensitivity / variability.

Fuses need substantial (by IC min-W device standards)
current and probably want to be kept out near the pads.
In 0.5um technology, the switch FET to blow a fuse comes
out about bond pad sized. Much better at lower L nodes.
A flow that allows circuit-under-pad would be a bonus
(although the fuse neck has to be out from under, for
thermal properties, the rest of the fuse pad active ckty
could be sitting under "wasted space" - potentially even
a serial programming link plus N fuse-blow switches). If
you already have a serial interface (a more complex chip,
of which the Vref is only a small part) then maybe you
are down to just a rack of blow-switches under (say) a
power pad, with N fuses between it and the nearby GND
pad, and some bussing from the serial data register.

Fuse trim needs a "try before you buy" mode. Keep that
in mind, it will affect your close-in trim circuitry design.
A switch-based, digital controlled trim offers this easily.
I've made "solo" fuse pads which can be "tickled" (for
pre-trim-commit test) or "pounded" (for permanent),
before, that need no other resources.