how to implement a self maed IP block in Xilinx EDK 7.1?

[wouterdetuinkabouter]

Hello,

We are working on our graduatingwork and we are having some difficulties.
We made a block in Simulink and now we trie to add it in EDK as a IPBLOCK.
But when we do so, de block has no connections. When we want to connect it we are getting a lot of errors.
Here is the project, can someone implement the block and tell us how it works, because later we have to implement a FIR filter.
THX


Greetz,

PS de block that needs to added is andee it is a and in VHDL made with Simulink.

 

[Manny_Calavera]

wouterdetuinkabouter,

Xilinx has recently released a new product called PlanAhead. Amongst many things it features the ability to create your own IP blocks based on your synthesized designs. The tool comes with a 30 days fully-functional trial period which I figure is enough for your needs. There is a slight learning curve associated with it, still I think it's a pretty novel cool software tool from xilinx that is even worth buying.

Cheers.