How to identify verilog compiler at compile-time?

[echo47]

`ifdef modelsim

Do Verilog compilers (ModelS!m, Synpl!fy Pro, and XST) provide any predefined values that can be tested at compile-time (perhaps by using `ifdef statements) to determine which compiler is being used?

C compilers usually provide a macro such as __MSVC__ or __GNUC__ that identifies the compiler, but I can't find anything like that in Verilog compilers.

As a workaround, I could probably set a value with a command line parameter, but I'd prefer to use a predefined value provided by the compiler.

Thanks.

 

[CatKing]

Yes, you can do like this:

`ifdef MODELSIM
$Some_ModelSim_PLI();
`endif

 

[echo47]

That's what I thought too, but MODELSIM seems to be an undefined macro. Using SE 5.7g.