NQ21HT449
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This supposed low technical risk project turned into disaster. I've asked Analog but they were not able to help me.
Essentially, I've replaced old PLL and PDF with ADF4002 integrated PLL and PFD and the new PLL has significantly worse phase noise performance so that I can't meet the specs of the old PLL.
This is the 10.7 MHz reference signal, it's generated by DDS and is AC coupled via transformers into F_REF pin of ADF4002:
Registers are programmed as following for both, old PLL and a new PLL: PFD = 100 kHz /R = 107, /N = 514, CP current is set to 5 mA on a new PLL.
VCO is the same for both, old and new PLL. Output of VCO with old PLL:
And VCO output with new PLL (ADF4002):
The schematic for PLL was based on page 5 of this technical note from Analog
This is the circuit of the new PLL:
Active loop filter was varied to the extremes, but I couldn't come up with a solution that addresses phase noise issue. For loop op amp, we've used OP184, ADA4625, and AD8065, neither of which seemed to contribute to phase noise. When VCO is tuned to a different frequency, I measure similar data - the fifth harmonic of reference spur (60 Hz * 5) at 300 Hz on both sides of LO is the highest spurious signal. We've tried to reduce 60 Hz tone from power supplies, but the couldn't improve over existing filtering.
This was supposed to be low technical risk project, VCO was kept exactly the same, voltage regulators were the same, except ADM7155ARDZ-04-R7 (very clean) was added to supply VDD of the new PLL. New PLL was placed in the same spot old PLL resided, VCO control lines were as short as possible.
Either way, with new PLL we can't meet any transmitter or receiver specs, other than scrapping the entire project, is there anything I can try to salvage this?
ADF4002 significantly increases phase noise at lower offset - Q&A - RF and Microwave - EngineerZone
Hello, this is the issue we are trying to resolve for several months already. If you could get me in touch with someone from Analog who is familiar with this IC
Essentially, I've replaced old PLL and PDF with ADF4002 integrated PLL and PFD and the new PLL has significantly worse phase noise performance so that I can't meet the specs of the old PLL.
This is the 10.7 MHz reference signal, it's generated by DDS and is AC coupled via transformers into F_REF pin of ADF4002:
Registers are programmed as following for both, old PLL and a new PLL: PFD = 100 kHz /R = 107, /N = 514, CP current is set to 5 mA on a new PLL.
VCO is the same for both, old and new PLL. Output of VCO with old PLL:
And VCO output with new PLL (ADF4002):
The schematic for PLL was based on page 5 of this technical note from Analog
This is the circuit of the new PLL:
Active loop filter was varied to the extremes, but I couldn't come up with a solution that addresses phase noise issue. For loop op amp, we've used OP184, ADA4625, and AD8065, neither of which seemed to contribute to phase noise. When VCO is tuned to a different frequency, I measure similar data - the fifth harmonic of reference spur (60 Hz * 5) at 300 Hz on both sides of LO is the highest spurious signal. We've tried to reduce 60 Hz tone from power supplies, but the couldn't improve over existing filtering.
This was supposed to be low technical risk project, VCO was kept exactly the same, voltage regulators were the same, except ADM7155ARDZ-04-R7 (very clean) was added to supply VDD of the new PLL. New PLL was placed in the same spot old PLL resided, VCO control lines were as short as possible.
Either way, with new PLL we can't meet any transmitter or receiver specs, other than scrapping the entire project, is there anything I can try to salvage this?