How to identify and reduce phase noise at low offsets introduced by PLL (ADF4002)?

[NQ21HT449]

This supposed low technical risk project turned into disaster. I've asked Analog but they were not able to help me.

ADF4002 significantly increases phase noise at lower offset - Q&A - RF and Microwave - EngineerZone

Hello, this is the issue we are trying to resolve for several months already. If you could get me in touch with someone from Analog who is familiar with this IC

ez.analog.com

Essentially, I've replaced old PLL and PDF with ADF4002 integrated PLL and PFD and the new PLL has significantly worse phase noise performance so that I can't meet the specs of the old PLL.

This is the 10.7 MHz reference signal, it's generated by DDS and is AC coupled via transformers into F_REF pin of ADF4002:

Registers are programmed as following for both, old PLL and a new PLL: PFD = 100 kHz /R = 107, /N = 514, CP current is set to 5 mA on a new PLL.

VCO is the same for both, old and new PLL. Output of VCO with old PLL:

And VCO output with new PLL (ADF4002):

The schematic for PLL was based on page 5 of this technical note from Analog

https://www.analog.com/media/en/reference-design-documentation/reference-designs/CN0369.pdf

This is the circuit of the new PLL:

Active loop filter was varied to the extremes, but I couldn't come up with a solution that addresses phase noise issue. For loop op amp, we've used OP184, ADA4625, and AD8065, neither of which seemed to contribute to phase noise. When VCO is tuned to a different frequency, I measure similar data - the fifth harmonic of reference spur (60 Hz * 5) at 300 Hz on both sides of LO is the highest spurious signal. We've tried to reduce 60 Hz tone from power supplies, but the couldn't improve over existing filtering.

This was supposed to be low technical risk project, VCO was kept exactly the same, voltage regulators were the same, except ADM7155ARDZ-04-R7 (very clean) was added to supply VDD of the new PLL. New PLL was placed in the same spot old PLL resided, VCO control lines were as short as possible.

Either way, with new PLL we can't meet any transmitter or receiver specs, other than scrapping the entire project, is there anything I can try to salvage this?

 

[BigBoss]

There might be many reasons that disturb to functionalty of the PLL.
They are not Phase Noise Related, they are just Spurious and this can have many cause including layout, supply, grounding, reference, EMI etc.
Nobody here can answer you without seeing layout and how it's been implemented.

 

[NQ21HT449]

There might be many reasons that disturb to functionalty of the PLL.
They are not Phase Noise Related, they are just Spurious and this can have many cause including layout, supply, grounding, reference, EMI etc.
Nobody here can answer you without seeing layout and how it's been implemented.

The spurs also appear in the old design. I'm not trying to eliminate them completely, I just need to reduce that level. Looking at the noise floor in the new design, I see it's raised ~20 dB, increasing both, noise floor and spurs that appear there. My logic was, therefore, if I reduce that hump, the spur level would also drop by the same amount in dB.

edit: Also, I've searched forum for this topic and measured some things that @BigBoss suggested, like letting VCO run unlocked to see the spurious level. Unlocked VCO doesn't have that hump at 300 Hz, so definitely, the PLL is creating this offset.

Is it possible that there's something fundamentally incompatible between this particular PLL and JFET-based VCO?

 

[rf_engineer_5]

ADI makes an eval board for this PLL chip. Is it possible you have it and do a comparison to yours? ADI usually does a pretty good job with their eval boards. If anything your layout should mimic theirs as a starting point. As asked above, seeing the layout would be helpful as well as the signal chain (block diagram should be ok if proprietary in nature).

Is it possible to swap out to a different VCO? I realize this is a task as tuning constant and loop filter has to be recalculated but if you want to know if there is interaction in the setup you have now this would be one way to do it.

 

[volker@muehlhaus]

Apologies for this simple question, but have you double checked the actual values of the loop filter against the ADIsim calculation?
The entire phase noise curve reminds me of a PLL with too small loop bandwidth. But you have designed for 2.5KHz, so are the placed component values all correct?

 

[NQ21HT449]

ADI makes an eval board for this PLL chip. Is it possible you have it and do a comparison to yours? ADI usually does a pretty good job with their eval boards. If anything your layout should mimic theirs as a starting point. As asked above, seeing the layout would be helpful as well as the signal chain (block diagram should be ok if proprietary in nature).

Is it possible to swap out to a different VCO? I realize this is a task as tuning constant and loop filter has to be recalculated but if you want to know if there is interaction in the setup you have now this would be one way to do it.

We have tested our VCO with their eval board, and we've had issues with phase noise back then. Then the logic was that perhaps, the wires forming feedback loop, that connect eval board to VCO (even though we shielded them with brass and grounded well) could pick up noise from environment that is increasing this phase noise floor. What we did then was new board layout, so that VCO and PLL are on the same board, with proper grounding and short traces. This is where we are at now, this did not resolve the issue.

As far as swapping VCO, this is what I'll end up doing if I can't get this fixed. At that point, I'll throw away ADF4002 in the garbage, as well as DDS, and use one of the integrated PLL + VCO ICs from TI. This is practically starting this project from scratch.

--- Updated Aug 21, 2024 ---

Apologies for this simple question, but have you double checked the actual values of the loop filter against the ADIsim calculation?
The entire phase noise curve reminds me of a PLL with too small loop bandwidth. But you have designed for 2.5KHz, so are the placed component values all correct?

We've designed loop filter to be 2.5 kHz (so that rule of thumb of loop filter BW <= PFD/10), but we've tried 1 kHz, 5 kHz, 10 kHz, which all either don't resolve the issue or even raise phase noise at different offsets. But to answer your question, yes, this design in ADISimPLL that I've attached here is exactly what's on the board.

 

[rf_engineer_5]

How did the ADI eval perform with their default VCO? Was the phase noise/noise present better than what you have now? Probably two different frequencies of operation here but if the performance with the default VCO looked good and met your spec (even though it may be the wrong frequency), chances are the problem is the VCO in your present case. For quick and dirty VCOs replacements you could try a MEMS VCO or you might get lucky with an in stock VCXO at the usual suspects like digikey or mouser.

 

[NQ21HT449]

How did the ADI eval perform with their default VCO? Was the phase noise/noise present better than what you have now? Probably two different frequencies of operation here but if the performance with the default VCO looked good and met your spec (even though it may be the wrong frequency), chances are the problem is the VCO in your present case. For quick and dirty VCOs replacements you could try a MEMS VCO or you might get lucky with an in stock VCXO at the usual suspects like digikey or mouser.

I mentioned in this thread that I let VCO run unlocked (control voltage disconnected), and it doesn't have the issue with phase noise. So I know that PLL is creating it, not my VCO.

 

[D.A.(Tony)Stewart]

What are the values of the fractional-N loops?

 

[NQ21HT449]

What are the values of the fractional-N loops?

Excuse me, what are "fractional-N loops"? We're using integer-N and /R = 107, /N = 514.

 

[D.A.(Tony)Stewart]

There are 2 counters.
Dividing the output for feedback, N is a multiplier.
Dividing the reference clock as a divider, R gives you the fraction N/R, and changing either one periodically adds another fraction. using Clk & Data registers.

Multiplication by N raises the signal’s phase noise by 20Log(N) [dB]

That is a simple description of Fractional-N.

details

https://www.ti.com/lit/an/swra029/swra029.pdf

You have Intermodulation spurs from the counters. Each counter stage makes current noise on Vdd. (xx pF x Ohms)
Check Vdd noise using AC couple 50-ohm coax terminated at DSO or better a Spectrum Analyzer or both.
Report results.

Verify all : DVdd and AVdd and Dgnd and Agnd.

Find out if it is lack of decoupling on IC by the impedance of the cap at RF getting into the mixer somehow by conduction from Vdd or Vss. or by parasitic ESL or C into the mixer.

My 1st bet is on the decoupling caps, 2nd is on charge pump routing, caps gnd shift etc. 3rd is routing on supply/returns.