Create a schematic with a couple of hundred short unconnected nets, then you can work around the gate array doing esc (edit select connected copper) and then assign a net name to each selection (It might even be scriptable)?
Actually, create a schematic sheet with the appropriate fpga on it with each pin having a small net of sane name, that way you can assign meaningful names to nets.
The other approach to this sort of thing is to find the jtag pins and use boundary scan to figure out what is on the jtag loop and what you can trace out that way.
Regards, Dan.