mic_huhu
Member level 3
![Member level 3](/styles/images/ranks/dlevel3.gif)
Hi,all
How to handle this case?
My design has a system asychoronous reset ,and only one submodule has a module asychoronous reset from another module. other submodules share this system asychorounous reset.
How to handle the submodule asy reset in DC synthesis?
and whether this design has a disadvantage?
Thanks
Johnny
How to handle this case?
My design has a system asychoronous reset ,and only one submodule has a module asychoronous reset from another module. other submodules share this system asychorounous reset.
How to handle the submodule asy reset in DC synthesis?
and whether this design has a disadvantage?
Thanks
Johnny