[SOLVED] How to handle signals generated from Finit State Machine?

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LatticeSemiconductor

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Hi,

i have a bunch of signals generated from a FSM. I want to use those to trigger certain operations, so i did the following:
Code VHDL - [expand]
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signal var : std_logic; -- output from FSM
 
process (var)
begin
   if rising_edge(var) then
      cnt <= cnt + 1;
   end if;
end process;


and 

Code VHDL - [expand]
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process( CLK, RST, var )
  begin
    if RST = '1' then
      CLK_SIG          <= '0';
      VAR_PREV <= '0';
    elsif rising_edge (CLK) then
      VAR_PREV <= var;
      if VAR_PREV /= var then
        CLK_SIG <= not CLK_SIG;
      end if;
    end if ;
  end process ; 
 
process (CLK_SIG)
begin
   if rising_edge (CLK_SIG) then
      cnt <= cnt + 1;
   end if;
end process;


those are my solutions and both are working quite well. I wonder however if that is the correct way to code, or if there are any techniques i could / should apply in those cases. Can i use any signal for a rising_edge? var is not a clock signal with very irregular transitions, though it's synchronous with 'CLK'. Could this cause timing problems?
 
Last edited:

You shouldnt do that. Creating internal clocks is bad engineering.
Much better to create a clock enable, ie. var is only high for 1 clock cycle :

Code: 
process(clk)
begin
  if rising_edge(clk) then
    if var = '1' then
      cnt <= cnt + 1;
    end if;
  end if;
end process;

Logic generated clocks are prone to high skew and temperature variations, and make life difficult for the timing analysis. Just dont do it.
 


ads-ee said:
In both cases you are generating clocks using logic. This is not a good design practice in an FPGA. What you want to do is generate enables and use a single clock domain.
Click to expand...

I am using the medwedew-machine. There is a lot about FSM design on the internet, and i think my FSM is fine. Though, a FSM only consists of state-transitions and some bits as output. Now the counter on my previous code was only an example, but i have a couple of operations i pretend to do, mostly sequentially and controlled by the FSM. So, the most obviouse solution would be to output some enable signals. However, until some condition is true, no transition occure so my enable signal remain active for more than one clock cycle, unless i add states without condition in between to set those for one clk cycle.

if i create one cycle pulses from enable signal, and use that as enable in a clocked process - would that be a good solution?
 

TrickyDicky said:
Please explain what you mean, preferably with some code...
Click to expand...

for example, i am reading from sdram and waiting until a certain register contains a valid value. While waiting, i want to load other registers with the next values used on the following write operation. So, during the "wait state" i will have an enable signal for several clock cycles. to avoid the "todo-section" is executed for more than one clock period, i used following code:

Code VHDL - [expand]
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process (clk, reset) is
begin
  if reset = '1' then
    enable_ff <= '0';
  elsif rising_edge(clk) then
    enable_ff  <= enable_fsm; 
    if (enable_fsm = '1') and (enable_ff = '0') then 
      -- todo
    end if;
  end if;
end process;
 

aslong as it's inside the synchronous process thats clocked from the system clock - you can do whatever you want. The code you posted is just a rising edge detect, and is done quite frequently. Just make sure its readible for yourself after a 6month/2 year/ 10 year break. Add plenty of coments. Write appropriate documentation..

Nothing like picking up someone elses code with obscure signal names, no coments, no documentation and having to work out whats going on from the 20 processes in the file!
 

Only 20 processes in the file...boy Tricky you've had it easy...try a file that is over 1000 lines long not a shred of comments with signal names that look like a random selection of characters and/or names like x, ll, ab, s, etc.

LatticeSemiconductor, For common things like synchronization registers between clock domains, edge detectors (like what you wanted). I like to create common library component/modules that implement these functions and give the internal names of the registers something that can be easily found in the synthesized netlist. This can be very helpful when generating constraints.

Regards
 
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