How to Handle Bidirection I/Os in ATPG Pattern Generation

Hi All,

I was reading an article about scan planning

It said we should
"Handle bidirectional I/O with care.
Bidirectional I/Os can cause problems on
testers, depending on how freely the
ATPG tool chooses to operate them."

What does that mean?

How do we generally take care of BIdi I/Os?

Could someone please explain

Thanks,

normally, we fixe the dicrection during scan mode, to avoid any change direction, and to be able to made at speed test.
Changing direction reduce dramaticly the pad speed.

You have to be careful not to have a bidirect conflict while testing your chip. A bidirect conflict occurs when you have the inputs driving opposite values on to the bus. It might also be a problem if they drive the same value. Depends on technology I think.

While scanning the bidir enables are going to be toggling so to prevent bidirect conflicts you put Z on all bidirect pins or using the TEI pin to disable all bidirect outputs on the chip.

When a test is being applied to your chip you will need to ensure that values captured by the bidir enable flip-flops don't result in 2 drivers on the bidirect bus. Your ATPG might be able to prevent this or you could by forcing values on the circuit but it will result in lower test coverage. The easiest way to avoid this is add a TEI pin that disables all bidirect inputs. The tests can be formatted into 3 cycles, strobe, wait and clock. Where strobe checks values on output pins without application of a clock. Wait uses TEI to force the bidirects into input mode and provides time for the busses to change direction. In the clock cycle you have to maintain the value that was on the bus in the strobe cycle by driving the bidirect inputs and then apply the capture clock.