how to got whole PLL bandwidth

[fencl]

hi,
i'm a newer in pll, papers often told me the pll bandwidth should less than 1/10 of operation frequency. but how can i got the whole pll bandwidth with hspice? we take a basic pll for eg. vin is input ck,vref is feedback ck. and vout is output ck.
what kind of source should i set?since pll is a discrete system with no op point as opamp.

****
vin vin 0 dc ? ac 1
.ac dec 10 1 1g

i try like this source ,but the result seems incorrect.
Then how could i got it ?

 

[windknows]

maybe it is better to built the linear model in matlab and check the bode plot

hi,
i'm a newer in pll, papers often told me the pll bandwidth should less than 1/10 of operation frequency. but how can i got the whole pll bandwidth with hspice? we take a basic pll for eg. vin is input ck,vref is feedback ck. and vout is output ck.
what kind of source should i set?since pll is a discrete system with no op point as opamp.

****
vin vin 0 dc ? ac 1
.ac dec 10 1 1g

i try like this source ,but the result seems incorrect.
Then how could i got it ?

 

[love_analog]

you will have to create a linear model of all the PLL components and then you can plot it in spice giving it stimulus similar to what you showed below.

 

[biff44]

hi,
i'm a newer in pll, papers often told me the pll bandwidth should less than 1/10 of operation frequency. ?

Who told you that? Santa Claus?

So if you have a 20 GHz oscillator and you phase lock it, your PLL bandwidth sould be 2 GHz wide????

The loop bandwidth has NOTHING to do with the VCO oscillating frequency.

 

[AdvaRes]

Hi all,
Its true fencl, take a look here: