How to go about solving transistor sizing tasks?

[deepa]

Implement the equation X = ((A + B) (C + D + E) + F) G using complementary
CMOS. Size the devices so that the output resistance is the same as that of an inverter
with an NMOS W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst and
best equivalent pull-up or pull-down resistance?
this is a question from RAbaey,,there are many similar such sizing questions ,,how to go about solving them

 

[ahmad_abdulghany]

Re: transistor sizing

Dear deepa,

I can explain it to you easily, even size them to you, but if i did,you won't learn..
so, follow me, and you will do it at last, and be happy that i didn't do it for you

Well?

First, i want you to draw the schematic of the funciton you wrote.. tell me if you don't knwo how..

After drawing it, i will show you how to size both NMOS and PMOS, OK?

Best Wishes,
Ahmad,

 

[deepa]

Re: transistor sizing

yeah i do know how to create the schematic,,i donnot know how to proceed further,,
i have attached a file drawing of the schematic ,i have missed out the Vdd n Vss values ..

 

[ahmad_abdulghany]

Re: transistor sizing

Well done, but you missed to connect the G PMOS well

and concerning Vdd and Vss, consider them anything, it won't matter at all,

Say Vdd=3V, and Vss=0V...

Now, you have to know that sizing depends upon the critical path trainstors in both PMOS and NMOS circuits indvidually, i.e. you will size PMOS then size NMOS transistors as if thery're two separate problems.. ok?

Now, in the PMOS circuit, where's the path of SERIES transistors that will cause maximum delay if they're all ON together? Isn't it C-D-E-F ? it contains four series PMOS, then we will size it and other PMOS depending on it..

How? When two MOSFETS be in series, this is simlar to one transistor with double LENGTH, and same WIDTH, i.e. for four series mosfets with L=1 and W=1 (for example), the resultant W/L=1/4, to let it become 1 again, you have to increase W of the four transistors to 4, understood this?

The same concept applied on two parallel MOSFETS, but now W will be doubled with the same L, hence two parallel MOSFETs have W=1 and L=1 gives overall W/L=2/1 ...

Then, you will first size the critical path to have resultant W/L=1, apply the concept above (I will leave it to you to do)..

Now consider the two other branches, A-B branch, and G branch, they're parallel to a branch of equivalent size of ..... (you calculate it ), size it to be the same as it...

Now, you have the equivalent worst case path in the pull up network (PMOS) aspect ration W/L=1, to get it equal 6, simply, multiply each size you obtained by 6 ... that's it,

Apply the same concept on the PDN (NMOS)...

The attached paper may be helpful to you ...

I hope that helped you
Regards,
Ahmad,

 

[deepa]

Re: transistor sizing

so if i size the pmos transistors (C,D,E,F) as 4 (W/L)p as per what u have said ,then to size the A B which is in parallel to C,D,E so the effective resisitance of A and B in series shold be the same as that of C,D,E in series is it so ,then A and B shld be of size 4/1.5 (W/L)p is it ?so the size of G is (W/L)p eh ?

 

[ahmad_abdulghany]

Re: transistor sizing

Did you read the paper i attached? Read the sizing part and try to answer your question..

 

[deepa]

Re: transistor sizing

isnt this statement wrong
For VI = VL = 0.2V, NMOS VGS less than Vtn (triode).
when Vgs<Vtn it is cut off not in triode region,,this is present in the third page of the pdf,.,

 

[Shurik]

Re: transistor sizing

Hi!
I think what so !!!

 

[Shurik]

Re: transistor sizing

Hello !!!!
I think what so !

 

[deepa]

Re: transistor sizing

wat does these files contain ,,,i didn understant whether u r answering or askin

 

[ahmad_abdulghany]

Re: transistor sizing

wat does these files contain ,,,i didn understant whether u r answering or askin

The test.pdf.gz file contains the correct answer but PUN size is 2 and PDN is 1, to modify to 6 and 2, just multiply every MOSFET size by 3 in PUN and 2 in PDN.

To open the file (under Linux), type in terminal:

gunzip test.pdf.gz | acroread test.pdf

Best Wishes,
Ahmad,

 

[deepa]

Re: transistor sizing

Ahmad,

i still dont get this answer,,,if i use the formulae given in the pdf,,if the equivalent (W/L )p given in the solution's pdf(111.pdf)doesn calculate to 2(W/L)..
as per your explanation if i am only able to understand how C,D,E,F are getting values 4(W/L)and even that has to be multiplied by 2 ..isnt it ???
can u pls explain the solution..

 

[Shurik]

Re: transistor sizing

This easy !!!
When you have three transistors in series connected that it common long increased.
But width stay contant!
The circuit we shall convert as equal inverter
Therefore in order to Kp of three transistors became equal Kp eq of one transistor make next
Leq= 3*L Weq = W
see image !!!!

https://obrazki.elektroda.pl/59_1163773493.jpg