How to give high impedence in verilog

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achaleus

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hi all,
Is there any way to give high impedance in verilog. I tried to give 10'bZ, bufif0,bufif1.. but it is taking all one's(I say in post synth simulation) . I am using vertex 6 fpga..
 

Hi,

If you want to tristate then you can try "tri1" for pull up or "tri0" for pull down
 

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