I've worked on FPGA designs with nearly that many clocks before, 30+. Most of the problems with that many clocks is the number of control sets you end up with. Every combination of clock, reset, and clock enable results in a new control set. Minimizing those may actually help place and route and timing closure.
Some advice is to reduce the number of resets to only reset critical control logic avoid any resets on the datapath unless those signals affect control logic. Avoid enables if you can just let the pipeline run without stopping it (I know sometimes that can't be done).
Floor plan the logic that is at the highest clock frequency and try to isolate it to a single clock region if possible (i.e., try not to overlap two clock regions if it fits in one. Don't try and create placement constraints for everything, the tools will likely do a much better job if you just do the minimum of placement constraints to give the tools a good starting point.