atremp
Junior Member level 2
VHDL system task problem
As we knwo, in Verilog HDL, we use $time/#stime to return
the current simulation time,
In VHDL, how do we can get the current simutation time.
or are there system functions?
As we knwo, in Verilog HDL, we use $time/#stime to return
the current simulation time,
In VHDL, how do we can get the current simutation time.
or are there system functions?