[SOLVED] how to get optimum noise impedance using spectre?

[lijulia]

spectre nfmin

Is it Gmin?

 

[sergio mariotti]

spectre zm1 z11

coud you give us more details?
Please explain more explicitally

 

[Mazz]

spectre　power　dissipation

If I well remember, performing S parameter simulation and enabling noise calculation, some results are available such as NFopt, but I'm not sure that Ropt is available. For sure is not Gmin.
Mazz

 

[frannk]

When a new device is fabricated, the Nopt is found by trial and error using very low loss stub tuners. I guess the same procedure can be applied to Spectre(not recommended). According to some old seasoned engineers I've dealt with, a good rule of thumb is that Nopt is about half way between Gopt and the center of the Smith chart.

 

[v_naren]

do a s-parameter analysis.
then goto results->direct plot->s-paramter then choose the item called as noise circles. then u can plot the noise circle for a noise figure = NFmin. the nfmin can be got from plotting NFmin directly. then u will not get a circle but a single point on the smith chart. Now just move ur mouse pointer over to this point and read off the optimum noise impedance
thats it..simple.....u just need to use the fundamentals and use simulator to help you

best of luck

do reply if u need help

I will explain in more detail

 

[lijulia]

Thanks v_naren!

But what is Gmin, from the spetre manual, Gmin is the reflection coefficient associated with minimum noise figure, is it the same thing as you get?

Also, when I get the NFmin and plot NC (noise circle), how do you specify a freq, instead of a freq. range?

For LNA design, how do you get the transistor size (BJT) for the Ropt?


Also, seems nobody use additional on-chip inductor for emitter degeneration instead of using direct down bondwire (0.5nH), right? Because if you calculate Le=Rs/WT=50ohm/40GHz=0.2nH for input matching to 50ohm, so if the bondwire 0.5nH > 0.2nH, then we will get lager input impedance not 50ohm , right?

Can you tell me more detail about the SiGe BJT LNA design procedure?

 

[v_naren]

1) Just as you correctly said Gmin is the reflection co-efficient associated with the minimum noise figure.(Gamma for minimum NF ref coeff). When I plotted Gmin and I moved my cursor over the curve you get the normalized impedance values over the frequency range...meaning I got Zopt/50.

2) Regarding the NC...when u choose NC option just choose Noise Level
instead of "frequency" to sweep in the "S-Parameter" results dialog box. Then u only need to enter one frequency. You can enter a range of values of the noise figure to get the noise circle plots. Now here if you
enter noise figure range as say 0 to 5 (dB) then ur 0dB noise circle will be a point as you may already know. Then this point would give me the optimum noise impedance.

3) I dont know if I understand your question correctly. what do you mean by getting transistor size(BJT) for a specific Ropt???......so do u mean u have a specifc value of Zopt and u want to find a BJT that will have its Zopt same as your requeired Zopt???.....ok if this is the case then there is a way out. Do you have a scalable BJT model file??.....Then do a parametric analysis using Affirma and sweep the emitter area...I hope by changing size of the BJT u mean changing its emitter area???..I am totally into CMOS LNAs!!!!.....so anyway if u have a scalable model then do a parametric analysis by sweeing the emitter area and then plot the Zopt...now check and see from the plot of Gmin as to which transistor's Gmin is closest to your required Gmin(Zopt) at the frequency you want.

4) ok...yes you are correct...but there is a way around this problem... ...what you can do is....place an Ls>0.2nH.........then the real part of input impedance will be wt*Ls>50Ohms...right?!!!...

example say u use an onchip inductor of value= 1.5nH

then with wt=40GHz and Ls=1.5nH
Zin=wt*Ls+ jw(Ls+Lg) + (1/jwCbe)

now u will get wt*Ls=377Ohms....now what u can do is add another matching network between the base of the BJT and the 50Ohm source to convert this 377+j.... to 50Ohm...now u need not use bondwire as u have deliberately used larger Ls and u will be using another simple LC matching network to convert the large 377+j... to 50Ohm. this can be done using the smith chart to design.

I design CMOS LNAs and hence I know the optimum device width and all..but the design procedure is same for both....I dont know if there is an optiumum device size for minimum noise figure for SiGe based LNAs....u cn try Prof.thomas Lee's book for reading CMOS based LNAs using the inductive source degeneration technique....byebye

 

[Mazz]

Very well explained v_naren!
And, as well, I've said a stupid thing saying: For sure is not Gmin. I've checked and you're right. Next time...first verify then...
Mazz

 

[lijulia]

Thanks you, v_naren!

But if you put larger on-chip inductor, of course you can always match to 50 ohms, but you will have larger Re Zin, will you get more noise? Is it a optimum design procedure? Because I saw people choose the right device size and Le to make Re Zin =50ohm then just use Ls to cancel the
Im Zin.

Also, another question, when I sweep the transistor size, then I should make Re Gmin =50ohm,
but I am pretty confused with Z11 and also ZM (port input impedance), seems eventually we care about the Zin not Gmin to match to 50ohms, right? Do I need to make Re ZM1 or Re Z11 to 50 ohm instead of Re Gmin? What's the difference between Z11 & ZM?

 

[v_naren]

1) I feel that I did not explain very well...I said use a bigger inductor in the source so that u get Re(zin)>50...its ok...then u use an L shape matching network to make the Re(Zin)=50 at the input of this impedance matching network. meaing u first use a big inductor in the emitter then u use another L,C network to make the ultimate Zin=50+j0. This will not introduce extra noise ideally...as all are lossless elements

2) u dont make Re(Z11) or Re(gmin)=50!!!!

u make Zin=50. thats all...and u automatically get the minimum noise figure for the optimum device width


Please refer A 1.5V 1.5GHz CMOS Low Noise Amplifier by Thomas H. Lee and Derek Shaeffer in JSSC....I dont think u understand LNA design well enuf...for me to try to explain the last parts....best of luck

 

[lijulia]

I think you misunderstanding my question.

I know you match Zin to 50ohm, but how do you measure Zin? you run sp analysis using spectre then look at Z11 (Re & IM) or ZM1 , right?

And also, for LNA design, I think they are using some design method for simultaneous noise and power matching of the transistor. They sweep the thansistor size(emitter length) to get the Re(Gmin) =50ohm, then choose Le to make Re(Zin)=50ohm. My question is, when I sweep the transistor size to find the right size for RE(Gmin)=50ohm, can I use Re(Z11) or Re(ZM1) also to find the transistor size? I am confused about the Gmin & Z11 here.

Also for the noise issue, I made a mistake, even for larger Le to get larger Re(Zin), the NF should be same, because Le just add equevinent resistor, not physical resistor. Just rb is real resistor who contribute noise.

 

[v_naren]

yes correct...this is the way!!!!!

here is what u need to do....

just make induc src degen stages with as many BJTs as u can....u cannot sweep anything here on!!!!!...

u need to put in BJT1 and Le1 and BJT2 and find Le2....all the time such that Re(Z11)=50Ohm....and always such that the DC power dissipation is a constant with each BJT means u need to change the bias voltage everytime...example..if u say u are going to burn 20mW...then u make sure that the DC power is 20mW with every BJT.

now u need to find the noise figure each time .....the noise figure will reach a minimum for a particular size of BJT. Thats all

now just use this "optimum size" BJT to make ur LNA. with a large inductor at emitter Le...example say you put Le=2nH.

then lets say u get input impedance at base as 200 + j 67 Ohm

now just use a passive lossless L matching network to convert this to 50 +j 0 or rather as 50Ohms.....thats all is the procedure...u can do the band pass thing at the collector of the cascode...and u get a LNA


the theory from the paper is that

for a given DC power dissipation there is only one MOSFET with a certain device width in one technology at any given frequency.

so for a 0.18um CMOS process at 2.45GHz...the MOSFET with Width of 420um will give best least possible noise figure...this is the concept....I just gave u a trick or "technique" to find that optimum size but in a BJT using the simulator itself...ita my own trick...I dont know for a BJT if there exists an optimum device size at all???...cuz I design CMOS LNAs in my research only

 

[dd2001]

4) ok...yes you are correct...but there is a way around this problem... ...what you can do is....place an Ls>0.2nH.........then the real part of input impedance will be wt*Ls>50Ohms...right?!!!...

example say u use an onchip inductor of value= 1.5nH

then with wt=40GHz and Ls=1.5nH
Zin=wt*Ls+ jw(Ls+Lg) + (1/jwCbe)

now u will get wt*Ls=377Ohms....now what u can do is add another matching network between the base of the BJT and the 50Ohm source to convert this 377+j.... to 50Ohm...now u need not use bondwire as u have deliberately used larger Ls and u will be using another simple LC matching network to convert the large 377+j... to 50Ohm. this can be done using the smith chart to design.

I design CMOS LNAs and hence I know the optimum device width and all..but the design procedure is same for both....I dont know if there is an optiumum device size for minimum noise figure for SiGe based LNAs....u cn try Prof.thomas Lee's book for reading CMOS based LNAs using the inductive source degeneration technique....byebye

Hi, it's very interesting.

Can you give me a sample for the LC matching network? I have same problem to be solved.

for 50 Ohms input matching, I got 0.2nH for Ls, however, bondwire has 1nH inductance, we really don't need it, it's extra inductance! How to eliminate this 1nH by LC matching you mentioned.

Thanks.

 

[v_naren]

what is your input impedance now with a 1nH inductor?

just use a simple L-Shaped LC matching network...dont you know how to do impedance transformation using L and C??

please refer RF circuit design by Chris Bowick or the one by Les Besser both of which are available here it elektroda....This will help transform the input impedance seen at the gate of the MOSFET from your larger value to 50OHMs using this.

 

[dd2001]

thanks v_naren.

Should we add this extra matching network on chip or out of chip?

 

[v_naren]

you can add it on chip or off-chip...I dont know why you ask this specifically?

I suggest u add it off chip if possible...as then once u fabricate the IC then u can get the exact Zin and then use external L and C safely to achieve the 50Ohm matching at the main input which will be out side now.

 

[David2004]

yes correct...this is the way!!!!!

here is what u need to do....

just make induc src degen stages with as many BJTs as u can....u cannot sweep anything here on!!!!!...

u need to put in BJT1 and Le1 and BJT2 and find Le2....all the time such that Re(Z11)=50Ohm....and always such that the DC power dissipation is a constant with each BJT means u need to change the bias voltage everytime...example..if u say u are going to burn 20mW...then u make sure that the DC power is 20mW with every BJT.

now u need to find the noise figure each time .....the noise figure will reach a minimum for a particular size of BJT. Thats all

now just use this "optimum size" BJT to make ur LNA. with a large inductor at emitter Le...example say you put Le=2nH.

then lets say u get input impedance at base as 200 + j 67 Ohm

now just use a passive lossless L matching network to convert this to 50 +j 0 or rather as 50Ohms.....thats all is the procedure...u can do the band pass thing at the collector of the cascode...and u get a LNA


the theory from the paper is that

for a given DC power dissipation there is only one MOSFET with a certain device width in one technology at any given frequency.

so for a 0.18um CMOS process at 2.45GHz...the MOSFET with Width of 420um will give best least possible noise figure...this is the concept....I just gave u a trick or "technique" to find that optimum size but in a BJT using the simulator itself...ita my own trick...I dont know for a BJT if there exists an optimum device size at all???...cuz I design CMOS LNAs in my research only

I am interest in the "420um" of MOSFET, how did you set the Vgt? That will induce larger power consumption?

 

[v_naren]

420um is for the 0.18um CMOS process which I use...yes correct..it does consume a lot of power and hence u need to set vgs very close to Vth and hence ur input signal swing is limited at the bottom end by vgs-vt.

 

[David2004]

420um is for the 0.18um CMOS process which I use...yes correct..it does consume a lot of power and hence u need to set vgs very close to Vth and hence ur input signal swing is limited at the bottom end by vgs-vt.

I think that will strongly affect your linearity of your LNA design if the Vgs is very close to Vth; the ft at working point would be pretty low. Normally people set Vgt>=0.2V.