Assuming u have a silicon in hand, if u have a setup violation, u can still get around it by lowering the frequency. But if u have a hold violation is it possible to get across it at least to test the functionality of the chip. Is there any way/method for it...?
hi Nir Dahan
i think the qn is after chip is realiszed on silicon ,, thn u have some hold violation,,,,,
yep,, i too listend some time back that the change in temp ,,, increase in temp can increase the delay and can help in removing hold violation
If u have inserted some spare cells in ur design, using eco (engg. chage order) u cn use them as a hold fixing buffers with some changes in final netlist and accordingly the routing. It requires a small chage not a complete respin.
Take the product on silicon at a higher temperature and find the highest temperature at which it is properly functional. You can also lower down the operating voltage and find out the maximum value of voltage at which the design functions properly.
Ultimately you are losing some temp and voltage range for this hold violation