Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to get a voltage graph to display signal starting from 0 in proteus isis?

Status
Not open for further replies.

Sunny55

Full Member level 3
Full Member level 3
Joined
Sep 15, 2012
Messages
159
Helped
12
Reputation
24
Reaction score
12
Trophy points
1,298
Activity points
2,404
I need to get an output voltage graph to display from 0v-20v but in proteus isis it just show a flat line at the 20V. I am using analogue analysis. Can anyone tell me how to set the display to start from 0 please? Please help
 

Basic Operation


Piecewise Linear Generator Type.

Having drawn the schematic, you choose the type of circuit analysis you require (transient, frequency, noise, etc.) by placing a Graph of the appropriate type on the schematic. You can place as many graphs as you want and can even have several graphs of the same type if you wish. Graph types supported include: Analogue, Digital and Mixed transient graphs as well as Frequency, Transfer, Noise, Distortion, Fourier, AC Sweep and DC Sweep and Audio graphs. The latter can be used to not only capture and display transient data but to also play it through a sound card.

Next, add and configure Generators to stimulate the circuit and Probes at points to be monitored. These can be dragged and dropped on the schematic like any other component and can also be reconfigured or dragged about between simulations. Analogue generators available include DC, Sine, Pulse, Piecewise Linear, File, Audio, Exponent and Single Frequency FM types and digital generators available include Edge, Pulse, Clock and Pattern types.


RS232 Serial Generator Data Scripted using EasyHDL.

Alternatively, you can write your own use script using Labcenter's EasyHDL (a BASIC like language) for greater control and flexibility over the injected signals. EasyHDL is a programming language which can be used to write scripts for testing complex test signals. We have christened this language EasyHDL as it is much simpler to learn and use than general purpose hardware description languages such as Verilog or VHDL. However, not withstanding its relative simplicity, EasyHDL can be used to generate both analogue and digital waveforms, and it can be used to create complex test vectors in which one script specifies the behaviour of multiple generator objects on the schematic. Another major benefit is that the scripts themselves can be debugged (breakpoints, single stepping, variables etc.) during simulation.

Finally you drag-and-drop one or more generators or probes on to a graph to choose what traces are displayed. A graph of a particular type with a given set of probes and generators is sufficient to tell ISIS and ProSPICE what part of the circuit to simulate, and what type of analysis to perform.

Post simulation you can maximise any graph, zoom in or out on the data as well as take timing, voltage and other measurements.



Conformance Analysis - A Unique Quality Assurance Tool

A conformance analysis compares one set of digital simulation results against another. The idea is that a design that has been previously accepted as working can be quickly re-tested after modification in order to prove that there have been no unwanted side effects arising from the change. This is particularly relevant in micro-controller based applications where the entire firmware program may need to be re-tested after changes have been made to the source code.

Conformance or non-conformance is determined by comparing the test and reference results at each edge of the first trace on the graph. Very significantly, there is no requirement for the edges in the test and reference copies of this control trace to occur at the same times. This means that changes in the absolute timing of events within the results data do not necessarily imply conformance. This is particularly relevent in micro-controller applications where any changes to the code will be bound to effect the absolute timing of events within the system. In such cases, the control trace may be generated by the code itself on entry and/or exit to the routines under test.


More info Please check this link **broken link removed**
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top