Feb 17, 2011 #1 B blaze1200 Newbie level 6 Joined Nov 23, 2010 Messages 13 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location Malaysia Activity points 1,350 Hi, My testbench is written in .cc format. What commands do i need to use in order to generate VCD file? (Via VCS) Thank you.
Hi, My testbench is written in .cc format. What commands do i need to use in order to generate VCD file? (Via VCS) Thank you.
Feb 17, 2011 #2 J Jack// ani Advanced Member level 3 Joined Dec 2, 2004 Messages 757 Helped 107 Reputation 222 Reaction score 58 Trophy points 1,308 Activity points 5,006 Re: Generate VCD file... Never heard of .cc format!! Is that Verilog or SV?
Feb 17, 2011 #3 B blaze1200 Newbie level 6 Joined Nov 23, 2010 Messages 13 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location Malaysia Activity points 1,350 Re: Generate VCD file... It is a C++ source file format.
Feb 22, 2011 #4 A avinashch Member level 2 Joined Oct 1, 2010 Messages 42 Helped 5 Reputation 10 Reaction score 5 Trophy points 1,288 Location california, usa Activity points 1,508 i dont know abt .cc format but if your testbench is in .v format just add $vcdpluson; after you declare your initials and your vcd file will be generated after simulation.
i dont know abt .cc format but if your testbench is in .v format just add $vcdpluson; after you declare your initials and your vcd file will be generated after simulation.
Mar 4, 2011 #5 B blaze1200 Newbie level 6 Joined Nov 23, 2010 Messages 13 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location Malaysia Activity points 1,350 Noted. Many thanks for the input.