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How to generate VCD file via VCS?

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blaze1200

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Hi,

My testbench is written in .cc format. What commands do i need to use in order to generate VCD file? (Via VCS) Thank you.
 

Re: Generate VCD file...

Never heard of .cc format!!

Is that Verilog or SV?
 
Re: Generate VCD file...

It is a C++ source file format.
 

i dont know abt .cc format but if your testbench is in .v format just add $vcdpluson; after you declare your initials and your vcd file will be generated after simulation.
 
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